AEW2015

Washington D.C.

Pinned Repositories

altera_examples
Examples for Altera FPGAs
Language:Jupyter Notebook6 2 01
fpga-colab
FPGA examples on Google Colab
Language:Jupyter Notebook19 4 04
fpga-miner
:moneybag: A simplified version of an FPGA bitcoin miner :moneybag:
Language:VHDL8 3 06
FPGA_RPi_Blade
A affordable HPC FPGA platform with COTS parts.
Language:Tcl11 4 02
FPGA_Zealot
FPGA Zealot Website Repo
5 4 00
PYNQ_PR_Overlay
Adding PR to the PYNQ Overlay
Language:VHDL17 6 29
SAFE
SEU-Aware FPGA Examples (SAFE) for Space 2.0
4 2 00
soft_riscv
Soft-core RISCV processor for RISCV 2018 competition
Language:C4 3 03
SPAS
Soft Processor Any% Speedrun
5 1 00
WARP_Core
Wilson AXI RISCV Processor Core
Language:VHDL7 8 02

AEW2015's Repositories

AEW2015/fpga-colab
FPGA examples on Google Colab
Language:Jupyter Notebook19 4 04
AEW2015/PYNQ_PR_Overlay
Adding PR to the PYNQ Overlay
Language:VHDL17 6 29
AEW2015/FPGA_RPi_Blade
A affordable HPC FPGA platform with COTS parts.
Language:Tcl11 4 02
AEW2015/fpga-miner
:moneybag: A simplified version of an FPGA bitcoin miner :moneybag:
Language:VHDL8 3 06
AEW2015/WARP_Core
Wilson AXI RISCV Processor Core
Language:VHDL7 8 02
AEW2015/altera_examples
Examples for Altera FPGAs
Language:Jupyter Notebook6 2 01
AEW2015/FPGA_Zealot
FPGA Zealot Website Repo
5 4 00
AEW2015/SPAS
Soft Processor Any% Speedrun
5 1 00
AEW2015/SAFE
SEU-Aware FPGA Examples (SAFE) for Space 2.0
4 2 00
AEW2015/soft_riscv
Soft-core RISCV processor for RISCV 2018 competition
Language:C4 3 03
AEW2015/fpga_resets
Paper to read
2 3 00
AEW2015/pypci
PCI driver for python
Language:Python2 2 01
AEW2015/TS-hack
The hackers guide to digital design for the ThunderScope platform
Language:Verilog2
AEW2015/BNN-PYNQ
Language:Jupyter Notebook1 3 00
AEW2015/linux-on-litex-vexriscv
Linux on LiteX-VexRiscv
Language:Python1 2 00
AEW2015/litedram
Small footprint and configurable DRAM core
Language:Python1 2 00
AEW2015/liteeth
Small footprint and configurable Ethernet core
Language:Python1 2 0
AEW2015/litex
Build your hardware, easily!
Language:C1 2 0
AEW2015/litex-boards
LiteX boards files
Language:Python1 2 0
AEW2015/openFPGALoader
Universal utility for programming FPGA
Language:C++1 1 0
AEW2015/Vitis-AI
Vitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.
Language:C++1 2 0
AEW2015/warp_bench
table of benchmarks
Language:C1 2 0
AEW2015/WILSON
WILSON Deep Space Probe
Language:CSS1 3 0
AEW2015/522R
Language:Coq3 0
AEW2015/ArcticFox_Handwash_Tutorial
Language:VHDL1 0
AEW2015/blinky
Example LED blinking project for your FPGA dev board of choice
Language:Tcl
AEW2015/ccl_log
Language:SCSS3 0
AEW2015/DND-5e-LaTeX-Template
LaTeX package to typeset material for the fifth edition of the "world's greatest roleplaying game".
Language:TeX3 0
AEW2015/ve2302
VE2302 Space Guide
2 0
AEW2015/xous-core
The Xous microkernel
Language:Rust1 0