WARP_Core
Wilson AXI RISCV Processor Core
- Website Documentation shows all the steps I went through in designing and testing this project.
News
The Goal is design a working RISCV processor for the Artix-7 on the Arty Board
STEPS:
- EDAplayground for a System Verilog test bench and DUT
- Have test bench use UVM
- Move test bnech and DUT to open source software COCOTB, IVerilog, and GHDL
- Compare options
Schedule
Check website for updates
Info
This Project is now focused on designing a RISCV processor to use the AXI bus.
Try to keep projects to minimal
- bd.tcl, verilog/vhdl
Settings
Log
Moving away from designing my own processor from scratch
- Docs is for parts documentation and reference material
- Projects will contain the top level HDL for test and fun applications.
- Cores will hold all the completed cores.
This project is continuing from the Mimas V2 processor