This is a puzzle. Can I work out the fuse map of MAX V devices by feeding the Quartus tools and observing the outputs?
My experiments are being run in the following environment.
- User code
- Fuse count
- Generate pins
- Unused pins
- I/O features
- PCI compliance
- I/O modes
- LUT
- Generate fast out
- LAB clk1
- LAB s-load
- LAB a-clr1
- LAB clk2
- LAB a-clr2
- LC local line
- LAB interconnect limit
- LC data MUX playground and theory
- IOC output MUX playground and theory
- IOC enable MUX playground and theory
- LC direct-link
- LAB ena1
- LAB ena2
- LAB ena2 vs s-load
- LAB a-load
- LAB s-clr
- LAB s-load always
- LC a-load
- LAB interconnect MUX playground 1 and playground 2 and database
- LAB control
- LAB control MUX playground and theory
- Global network LAB playground and IOB playground and theory
- IOB interconnect MUX playground and database
- Global internal
- Global MUX playground and theory
- Global interconnect MUX playground
- C4 interconnect MUX playground and database
- R4 interconnect MUX playground and database
- C4 fuse map generate and theory and inverse
- R4 fuse map generate and theory and inverse
- Device pins
- LC register types
- IO standards
- LUT chain
- Security bit
- ISP clamp
- 6502
- SAP-1
- LC feedback
- Register chain
- megafunctions
- Carry chain 3 (4 , 5 , 9)
A mapping to and from fuse numbers, locations & names is encoded in fuse map.
The following mux mappings are encoded:
Some MUX databases have been collected:
- LAB interconnect MUX
database/*.lab-interconnect
- IOB interconnect MUX
database/*.iob-interconnect
- C4 interconnect MUX
database/*.c4-interconnect
- R4 interconnect MUX
database/*.r4-interconnect
This enables the device wide reset pin that resets all registers in the device
This enables the device wide output enable pin to control the output enable for every output pin on the device.
Each of the four global clock networks are driven horizontally (row) and then to each column. Unused clock networks are turned off either at individual columns or for the whole row.
Each of the global clock networks can be driven from either:
- dedicated pins, or
- internal interconnects.
This fuse selects the internal interconnects.
Selects an interconnect into each of the four global networks.
For the 5M240Z,
each global network has a two dimentional mux of size 6 x 3
selecting from 18 interconnects at {ioc,1,3}
.
For other densities,
each global network has a two dimentional mux of size 4 x 3
selecting from 10 interconnects
at {iob,9,3}
, {iob,11,3}
& {iob,13,3}
respectively.
Selects a direct-link, C4 or R4 onto the Global interconnect.
Each interconnect has a two dimentional mux of size 4 x 3 selecting from 12 alternative sources.
This does not exist on the 5M240Z,
it's global interconnect shares the interconnect of {iob, 1, 3}
.
There are 32 bits of user oode numbered LSB (0) to MSB (31).
The user code bits are stored in the POF file inverted,
so a user code bit of 1
is stored as a 0
.
Selects a direct-link from a neighbouring LAB onto an IOB's interconnect.
Only applicable for IOBs on the left and right sides.
Not used at the same time as the interconnect muxes below.
{iob(), {interconnect, #}, from4, mux#}
, {iob(), {interconnect, #}, from3, mux#}
and {iob(), {interconnect, 8/17}, from4, gclk}
Selects a direct-link, C4 or R4 onto an IOB's interconnect.
Not used at the same time as the dedicated direct-link above.
Each interconnect has a two dimentional mux of size 4 x 3 selecting from 12 alternative sources.
As a special case, row interconnects 8 and 17 have an extra fuse expanding the mux to size 5 x 3. The extra 3 alternatives source from the global clock networks.
The IOC input is turned off when the POF but is 0
.
This could also be called output only.
The IOC outputs are selected from local interconnects via two dimentional muxes. Side IOCs have one of size 3, and the other of size 6. Top/bottom IOCS have one of size 3, and the other of size 4.
These muxes are one-cold.
For example the fuses
{ioc(), output6, mux2}
and {ioc(), output3, mux1}
select local interconnect 7.
For example the fuses
{ioc(), output4, mux3}
and {ioc(), output3, mux2}
select local line 9.
Selects output value from fast-out link of neighbouring LAB instead of via the output muxes.
The IOC output is inverted when the POF but is 0
.
The IOC output enables are selected from local interconnects.
See {ioc(), output#, mux#}
for details.
The IOC is an output when the POF but is 0
.
Each IOC can have bus-hold or weak pull-up enabled.
The feature is enabled when the POF bit is 0
.
Warning: only enable one at a time.
Drive strength of IOC outputs can be minimum or maximum current.
Default drive strength is maximum current.
A low current strength is enabled with a POF bit of 0
.
NOTE: Both fuses are always the same as each other.
Slew Rate of IOC outputs is fast with a POF bit of 0
.
Input delay on IOC inputs enabled with a POF bit of 0
.
Open-Drain outputs enabled with a POF bit of 0
.
PCI compliant outputs enabled with a POF bit of 0
.
NOTE: Only avaailable in Bank 3 of 5M1270Z and 5M2210Z.
Schmitt Trigger on IOC inputs enabled with a POF bit of 0
.
NOTE: Also enabled when in output mode.
Selects a direct-link from a neighbouring LAB onto a LAB's interconnect.
Not used at the same time as the interconnect muxes below.
{lab(), {interconnect, #}, from4, mux#}
, {lab(), {interconnect, #}, from3, mux#}
and {lab(), {interconnect, 12/25}, from4, gclk}
Selects a direct-link, C4 or R4 onto a LAB's interconnect.
Not used at the same time as the dedicated direct-link above.
Each interconnect has a two dimentional mux of size 4 x 3 selecting from 12 alternative sources.
As a special case, interconnects 12 and 25 have an extra fuse expanding the mux to size 5 x 3. The extra 3 alternatives source from the global clock networks.
Each LAB's clk# can be selected fron the four global signals (0..3) or a control line.
These fuses form a one-shot mux with the active selection with a bit of 0
.
When the LAB's clk1 line is selected from a control line.
The specific control line selected is:
- a
0
bit selects 0, - a
1
bit selects 1.
The LAB's clk2 & a-load lines share a common control source.
When the LAB's clk2 / a-load line is selected from a control line.
The specific control line selected is:
- a
0
bit selects 3, - a
1
bit selects 2.
The LAB's clk# line is inverted.
This turns off the LAB's ena1 line. LC's are then continuously enabled.
This selects the LAB's ena1 line from either:
- a
0
bit selects control line 3 - a
1
bit selects control line 2
This inverts the LAB's ena1 line.
This turns off the LAB's ena2 line. LC's are then continuously enabled.
The LAB's ena2 & s-load lines share a common control source.
When the LAB's ena2 / s-load line is selected from a control line.
The specific control line selected is:
- a
0
bit selects 0, - a
1
bit selects 1.
The LAB's ena2 & s-load lines share a common inversion.
The LAB's ena2 / s-load line is inverted.
Only one of the two a-clr# lines can select from a global line.
This mux is common to those two lines and selected by {lab(), a_clr#, global}
.
These fuses form a one-shot mux with the active selection with a bit of 0
.
Turns of the LAB's a-clr# line.
The LAB's a-clr# line is selected from one of the global lines (also when off).
Alternatively the line is selected from a control line.
When the LAB's a-clr# line is selected from a control line.
The specific control line selected is:
- a
0
bit selects 5, - a
1
bit selects 4.
The LAB's a-clr# line is inverted.
The LAB's a-load line is selected from one of the control lines.
The LAB's a-load line is inverted.
The LAB's s-clr line is selected from one of the control lines.
The LAB's s-clr line is inverted.
When the LAB's s-clr line is selected from a control line.
The specific control line selected is:
- a
0
bit selects 5, - a
1
bit selects 4.
The LAB's s-load line is selected from one of the control lines.
It has a bit 0
when the s-load is disconnected or connected to a signal.
It has a bit 1
when the s-load line is a constant 1
.
The LAB's invert-a line (addnsub) is enabled.
When the LAB's invert-a line is selected from a control line.
The specific control line selected is:
- a
0
bit selects 3, - a
1
bit selects 4.
The LAB's carry-in is selected from:
- a
0
bit selects from the previous LAB`s carry-out signal, - a
1
bit selects from the LAB's invert-a control line.
Each LC can select between two LAB wide clocks, clk1 & clk2.
This fuse selects clk2.
Each LC can select between two LAB wide a-clrs, a-clr1 & a-clr2.
This fuse selects a-clr1.
It also elects out of the LAB's a-load line.
The LUT inputs data_a
, data_b
, data_c
& data_d
are
selected from local interconnects via two dimentional muxes,
one of size 3, and the other of size 6.
These muxes are one-hot.
For example the fuses
{lc(), data_a3, mux1}
and {lc(), data_a6, mux0}
select local interconnect 3.
For example the fuses
{lc(), data_c3, mux2}
and {lc(), data_c6, mux5}
select local line 7.
Each LC can feedback the register output into it's own LUT at data_c
.
This fuse enables that feedback.
NOTE: The normal data_c
selection can then only be used as a s_load
source.
Each LC can drive the LUT or register output to the local interconnect via it's local line.
This fuse selects the LUT output (instead of register output).
Each LC can drive the LUT or register output to the left and right via direct-links, fast-outs, R4s & C4s.
These fuses select the LUT output (instead of register output).
Most LCs can receive a carry-in from the "previous" LC.
The carry-in always comes into the data_c
input.
The "previous" LC to {lc, X, Y, N}
is:
{lc, X, Y, N - 1}
forN
in1..9
, otherwise{lc, X - 1, Y, 9}
forN
is0
.
NOTE: The carry-change can go across the whole row.
NOTE: The left most {lc, _, _, 0}
of each row cannot receive a carry-in.
Each LC can receive a LUT input from the LUT output of the previous LC.
The input always comes into the data_d
input.
The first LC in a LAB has this fuse, but not sure where that input comes from.
Each LC as a 16-entry LUT with a fuse per entry.
The fuse for LUT term a AND (NOT b) AND c AND d
is named {lc(), lut, a1b0c1d1}
.
The stored bit is the result of the lookup.
Each LC register can chain it's output directly to the next LC without using
the second LC's LUT. It enters the second LC just before the s-load
selection.
The first LC in a LAB has this fuse, but not sure where that input comes from.
The LC's s-clr & s-load lines are enabled.