ericsonj/verilog-format

How to align multiple modules in one file?

duskmoon314 opened this issue · 0 comments

I have code like this

module sha256_round(
    input [31:0] Kt, Wt,
    input [31:0] a_in, b_in, c_in, d_in, e_in, f_in, g_in, h_in,
    output [31:0] a_out, b_out, c_out, d_out, e_out, f_out, g_out, h_out
);

endmodule

module sha256_s0(
    input wire [31:0] x,
    output wire [31:0] S0
);
endmodule

module sha256_s1(
    input wire [31:0] x,
    output wire [31:0] S1
);
endmodule

module Ch(
    input wire [31:0] x, y, z,
    output wire [31:0] Ch
);
endmodule

module Maj(
    input wire [31:0] x, y, z,
    output wire [31:0] Maj
);
endmodule

after saving, it becomes this

module sha256_round(input [31:0] Kt,
                    Wt,
                    input [31:0] a_in,
                    b_in,
                    c_in,
                    d_in,
                    e_in,
                    f_in,
                    g_in,
                    h_in,
                    output [31:0] a_out,
                    b_out,
                    c_out,
                    d_out,
                    e_out,
                    f_out,
                    g_out,
                    h_out);
endmodule
    
    module sha256_s0(
        input wire [31:0] x,
        output wire [31:0] S0
        );
    endmodule
        
        module sha256_s1(
            input wire [31:0] x,
            output wire [31:0] S1
            );
        endmodule
            
            module Ch(
                input wire [31:0] x, y, z,
                output wire [31:0] Ch
                );
            endmodule
                
                module Maj(
                    input wire [31:0] x, y, z,
                    output wire [31:0] Maj
                    );
                endmodule

I prefer something like this

module A(
    input [31:0] a_in,
                 b_in,
                 c_in
);
endmodule

module B(
);
endmodule

Is it possilbe to get this function now?