Issues
- 0
Could it support systemverilog?
#36 opened by wuch10 - 1
Formatting the current line, when the Chinese word is in singular form, the trailing characters may become garbled.
#35 opened by aisangsangshu - 0
It dosen't work totally
#33 opened by cannotgetaname - 0
NEQ operator divided after formatting
#25 opened by CrackLewis - 0
- 0
Incorrect formatting with multiple modules
#31 opened by lsmolinski - 0
- 0
- 0
- 1
case bug with parameter
#8 opened by YunKaiSu - 1
formatter bug
#2 opened by carlodri - 5
- 0
grammar file
#23 opened by quantrpeter - 0
Odd formatting for end else begin
#22 opened by Suhail - 1
how to actually activate formatting?
#21 opened by r2com - 1
We are using verilog-format
#20 opened by quantrpeter - 1
- 1
pipeline
#19 opened by quantrpeter - 0
/bin folder should be updated
#18 opened by HuaHuaY - 0
if statement without end
#15 opened by camrbuss - 2
Chinese Encoding / Decoding Bug
#14 opened by z0gSh1u - 0
Comment lines should be left untouched
#12 opened by giothub-StefanTH - 0
How to align multiple modules in one file?
#10 opened by duskmoon314 - 0
Better support for package_import_declaration in the module_ansi_header
#9 opened by pdonahue-ventana - 0
Feature: align instance brackets
#7 opened by kdurant - 0
Why doesn' it work ?
#6 opened by bmVisionEE - 0
begin end bug
#5 opened by wangzhankun - 0
always block format
#4 opened by wangzhankun - 0
indentation in module with tasks
#3 opened by kazarynau - 1
indentation control for module instances
#1 opened by carlodri