ernstblecha/vcd2tikztiming

Issues

• Add arguments as interface

  #4 opened 6 years ago by ernstblecha
  1

• Signalnames need to be sanitized for LaTeX

  #8 opened 5 years ago by ernstblecha
  1

• Add default template within main program

  #7 opened 6 years ago by ernstblecha
  0

• Fix dependency on latexpand

  #6 opened 6 years ago by ernstblecha
  0

• Optional cleanup of created files

  #5 opened 6 years ago by ernstblecha
  0

• Verilog_VCD.py has to be present in the workdirectory

  #3 opened 6 years ago by ernstblecha
  0

• Add interface for setting scale

  #1 opened 6 years ago by ernstblecha
  0

• Add means to select a timewindow

  #2 opened 6 years ago by ernstblecha
  0