MIPS-Single-Cycle
Computer Assignment 2 of UT computer organization course. take a look at CA#2.pdf for more information.
This is a single cycle MIPS proccessor which supports the following instructions:
R-Type(Both Reg-Reg, and Reg-immediate): ADD, ADDC (carry) , SUB, SUBC (carry), AND, OR, XOR, MASK
Shift: SHL, SHR, ROL, ROR
Mem: SW, LW
Condition Branch: BZ, BNZ, BC, BNC (based on carry and zero registers)
Other controll instructions: JMP, JSB (implemented by a stack), RET (stack)
The proccessor has the following specifications:
A register file: 8 registers, word size = 8bits
Instruction length: 19 bits
Instructon memory: 4096 registers (19 bits)
Data memory: 256 registers (8 bits)
ALU: 8 bits, carry, and Z (zero) support
FlipFlops: C and Z