Barriers between compute calls
geor-kasapidi opened this issue · 5 comments
As far as i know, to ensure same memory read write order, user need to insert barrier call between compute dispatches. But i don't see any sign of high level barrier calls in IGL for buffers. This is intentional or kinda bug?
Hey @geor-kasapidi!
You're correct, the compute pipeline interface is currently in the early stages of development. Moving forward, we'll incorporate a more robust system for handling dependencies.
As a hotfix, I can recommend downcasting command encoders and buffers to their IGL/Vulkan implementation types (vulkan::ComputeCommandEncoder
and vulkan::Buffer
) and inserting all the necessary barriers manually using appropriate raw Vulkan commands.
ok, thx!
@geor-kasapidi Implemented here 1909bcb
wow, this is huge - thank you!
@geor-kasapidi You're welcome! Don't hesitate to submit proposals or PRs if you think there's anything else that is missing.