farzadfch

farzadfch's Stars

• CSL-KU/bru-firesim

  BRU: Bandwidth Regulation Unit for Real-Time Multicore Processors

  Language:Python31

• ccelio/Speckle

  A wrapper for the SPEC CPU2006 benchmark suite.

  Language:Shell8553

• ucb-bar/ccbench

  Memory System Microbenchmarks

  Language:C6124

• farzadfch/gem5-cache-partitioning

  Gem5 L2 Cache Partitioning

  95

• CSL-KU/SpectreGuard

  Data-centric defense mechanism against Spectre attacks. (DAC'19)

  Language:C117

• trigonak/ccbench

  A tool for measuring the cache-coherence latencies of a processor (i.e., the latencies of loads, stores, CAS, FAI, TAS, and SWAP).

  Language:C7520

• cnrv/rocket-chip-read

  Comment on the rocket-chip source code

  16844

• farzadfch/freedom

  Language:Scala32

• freechipsproject/chisel-bootcamp

  Generator Bootcamp Material: Learn Chisel the Right Way

  Language:Jupyter Notebook976278

• CSL-KU/gem5

  Language:C++31

• abejgonzalez/boom-attacks

  Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)

  Language:C31

• CSL-KU/detmem

  Language:Perl44

• riscv-boom/riscv-boom

  SonicBOOM: The Berkeley Out-of-Order Machine

  Language:Scala1.7k426

• riscv-non-isa/riscv-asm-manual

  RISC-V Assembly Programmer's Manual

  Language:Makefile1.4k238

• westerndigitalcorporation/RISC-V-Linux

  This repository provides a Linux kernel bootable on RISC-V boards from SiFive

  Language:C16134

• ccelio/riscv-hpmcounters

  A simple utility for doing RISC-V HPM perf monitoring.

  Language:C++1412

• CSL-KU/firesim-nvdla

  FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud

  Language:Python16131

• farzadfch/mult_booth_app

  Approximate Booth Multiplier

  Language:MATLAB73

• firesim/firesim

  FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility

  Language:Scala882231