fatimasaleem

Design & Verification Engineer

10xEngineersLahore, Pakistan

Pinned Repositories

core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
Language:Assembly0 0 01
cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
Language:SystemVerilog0 0 00
cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Language:Assembly2 0 06
chisel-tutorial
chisel tutorial exercises and answers
Language:Scala0 0 00
cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
Language:Python0 0 00
riscv-isa-manual
RISC-V Instruction Set Manual
Language:TeX00
riscv-tools
RISC-V Tools (ISA Simulator and Tests)
Language:Shell00
core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
Language:Assembly437 48 505220
cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Language:Assembly2.2k 91 1k679

fatimasaleem's Repositories

fatimasaleem/chisel-tutorial
chisel tutorial exercises and answers
Language:Scala0 0 00
fatimasaleem/cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
Language:Python0 0 00
fatimasaleem/riscv-isa-manual
RISC-V Instruction Set Manual
Language:TeX00
fatimasaleem/riscv-tools
RISC-V Tools (ISA Simulator and Tests)
Language:Shell00