/fpga-drive-aximm-pcie

Example designs for FPGA Drive FMC

Primary LanguageTclMIT LicenseMIT

FPGA Drive FMC Reference Designs

Description

This repo contains the example designs for the FPGA Drive FMC mated with several FPGA and MPSoC evaluation boards.

FPGA Drive FMC top side

Important links:

Requirements

This project is designed for version 2022.1 of the Xilinx tools (Vivado/Vitis/PetaLinux). If you are using an older version of the Xilinx tools, then refer to the release tags to find the version of this repository that matches your version of the tools.

In order to test this design on hardware, you will need the following:

  • Vivado 2022.1
  • Vitis 2022.1
  • PetaLinux Tools 2022.1
  • FPGA Drive FMC Gen4 - for connecting a PCIe SSD
  • M.2 PCIe Solid State Drive
  • One of the supported carriers listed here

Build instructions

Contribute

We strongly encourage community contribution to these projects. Please make a pull request if you would like to share your work:

  • if you've spotted and fixed any issues
  • if you've added designs for other target platforms
  • if you've added software support for other devices

Thank you to everyone who supports us!

About us

Opsero Inc. is a team of FPGA developers delivering FPGA products and design services to start-ups and tech companies. Follow our blog, FPGA Developer, for news, tutorials and updates on the awesome projects we work on.