fei-g

ariane

Ariane is a 6-stage RISC-V CPU capable of booting Linux

fei-g.github.io

litedram

Small footprint and configurable DRAM core

litex-boards

LiteX boards files

openpiton

The OpenPiton Platform

SoftMC

SoftMC is an experimental FPGA-based memory controller design that can be used to develop tests for DDR3 SODIMMs using a C++ based API. The design, the interface, and its capabilities and limitations are discussed in our HPCA 2017 paper: "SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies" <https://people.inf.ethz.ch/omutlu/pub/softMC_hpca17.pdf>

tensorflow

Computation using data flow graphs for scalable machine learning

litex-boards

LiteX boards files

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

openpiton

The OpenPiton Platform

fei-g/SoftMC

SoftMC is an experimental FPGA-based memory controller design that can be used to develop tests for DDR3 SODIMMs using a C++ based API. The design, the interface, and its capabilities and limitations are discussed in our HPCA 2017 paper: "SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies" <https://people.inf.ethz.ch/omutlu/pub/softMC_hpca17.pdf>

fei-g/ariane

Ariane is a 6-stage RISC-V CPU capable of booting Linux

fei-g/fei-g.github.io

fei-g/litedram

Small footprint and configurable DRAM core

fei-g/litex-boards

LiteX boards files

fei-g/openpiton

The OpenPiton Platform

fei-g/tensorflow

Computation using data flow graphs for scalable machine learning