Pinned Repositories
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机器学习实战python代码
00_Image_Rotate
视频旋转（2019FPGA大赛）
8-bits-RISC-CPU-Verilog
Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（**处理器）简单结构和Verilog实现。
996.ICU
Repo for counting stars and contributing. Press F to pay respect to glorious developers.
AhaM3SoC
SoC Based on ARM Cortex-M3
AHB2
AMBA AHB 2.0 VIP in SystemVerilog UVM
algorithm-prratice
Algorithms
The codes and my solutions to exercises from the book "Algorithms" (4th edition) by Robert Sedgewick and Kevin Wayne.
RiscSoC
RiscSoC 是一个芯片集成项目，包含了 Cortex-M0、Cortex-M3、MIPS、RISC-V、4-BIT 等内核的 SoC 集成，部分 SoC 使用的自己设计的内核
vlc_plat
verilog/systemverilog code for visible light communication platform
feifan1996's Repositories
feifan1996/RiscSoC
RiscSoC 是一个芯片集成项目，包含了 Cortex-M0、Cortex-M3、MIPS、RISC-V、4-BIT 等内核的 SoC 集成，部分 SoC 使用的自己设计的内核
feifan1996/vlc_plat
verilog/systemverilog code for visible light communication platform
feifan1996/AhaM3SoC
SoC Based on ARM Cortex-M3
feifan1996/arm-foss
Experiment in creating an ARM Cortex-M0 SoC using only open source tools. This was just moved here from https://bitbucket.org/vahidi/arm-foss/
feifan1996/automatic-verilog
automatic-verilog based on vimscript
feifan1996/basic_verilog
Must-have verilog systemverilog modules
feifan1996/Chainsaw
feifan1996/cm3soc-demo
SoC Demo Based on Cortex-M3 Softcore Processor
feifan1996/cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
feifan1996/Cores-SweRV
SweRV EH1 core
feifan1996/Cores-SweRV-EH2
feifan1996/CortexM0_SoC
Cortex M0 based SoC
feifan1996/CortexM0_SoC_Task
Step by step tutorial for building CortexM0 SoC
feifan1996/CPlusPlusThings
C++那些事
feifan1996/darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
feifan1996/DetectHumanFaces
Real time face detection based on Arm Cortex-M3 DesignStart and FPGA
feifan1996/Hand-Writing-Digital-Recognization-Based-on-FPGA
Hand Writing Digital Recognization Based on FPGA, we desiged a SoC embeded a Cortex M3 core and other peripherals，this SoC run a CNN. The SoC worked not bad in the end the success rate up to 90%。.
feifan1996/iob-cache
Verilog configurable cache
feifan1996/math
SpinalHDL Hardware Math Library
feifan1996/open-register-design-tool
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
feifan1996/opentitan
OpenTitan: Open source silicon root of trust
feifan1996/openwifi
open-source IEEE802.11/Wi-Fi baseband chip/FPGA design
feifan1996/polar-3gpp-matlab
Matlab simulations of the encoder and SCL decoder for the New Radio polar code from 3GPP Release 15
feifan1996/pyuvm
The UVM written in Python
feifan1996/raptor
Arm Cortex-M0 based Customizable SoC for IoT Applications
feifan1996/SimpleSoC
Very simple Cortex-M1 SoC design based on ARM DesignStart
feifan1996/SOC-Design-ARM-M0
This is a repo containing ARM-Cortex-M0 based SOC designs implemented on the Nexus-4-DDR , Nexus-4 and the ARTY - A7 FPGA platforms.
feifan1996/soc_scripts
soc integration script and integration smoke script
feifan1996/TRIDENT
A Hardware Implemented Poseidon Hasher
feifan1996/ventus-gpgpu
GPGPU processor supporting RISCV-V extension, developed with Chisel HDL