This repository hosts the project for open-source hummingbird E200 RISC processor Core.
The Hummingbird E200 (32bits RISC processor core) was developed by "武汉聚芯微电子有限公司" and "北京九天微星科技发展有限公司", supporting part of RISC-V instruction set.
The Hummingbird E200 core is a two-stages pipeline based ultra-low power/area implementation, which has both performance and areas benchmark better than ARM Cortex-M0+ core, makes the Hummingbird E200 as a perfect replacement for legacy 8051 core or ARM Cortex-M cores in the IoT or other ultra-low power applications.
To boost the RISC-V popularity and to speed up the IoT development in China, we are very proud to make it open-source. It is the first open-source processor core from China mainland with industry level quality and state-of-art CPU design skills to support RISC-V instruction set.
Our ambition is to make "Hummingbird E200" become next 8051 in China, please go with us to make it happen.
If there are any questions or problems, you can directly contact bobhu_riscv@163.com
The open-source Hummingbird E200 core can be a perferct candidate for the following fields:
- Replace legacy 8051 core for better performance.
- Replace Cortex-M core for lower cost.
- Also, the Hummingbird E200 core as a simple ultra-low power core and SoC, which is "蜂鸟虽小、五脏俱全", with detailed Docs and Software/FPGA Demos, hence, it will be a perfect example for lab practice in university or entry-level studying.
We have provided very detailed introduction and quick start-up documents to help you ramping it up.
The detailed introduction and the quick start documentation can be seen
from e200_opensource/doc directory.
By following the guidences from the doc, you can very easily start to use Hummingbird E200 processor core and demo SoC.
What are you waiting for? Try it out now!
-- The 1st official release, please clone this version if you want to use it
or reclone it (if you already cloned the earlier-test version).
-- Compared with earlier-test version, main updates includes:
---- Added the "A" extension for opensourced E203 core, to make it support
IMAC sub-set RISC-V ISA, which is more popularly supported by current
toolchain.
---- Updated the RTL Codes accordingly.
---- Updated the Docs accordingly, please see the "revision history" in the
Doc from `e200_opensource/doc` directory.
---- Updated verilog tb with random interrupt and bus-error insertion to make
more intensive. To support this, updated all the self-check tests accordingly.
Although the test become more intensive, the drawback is make the regression
simulation running very slower, so by default now it is turned off.
If you want to turn on them without caring the the regression speed,
you can hack the tb mannually (de-comment these `force` line from `tb/tb_top.v`)
or add macro `ENABLE_TB_FORCE` in simulation (see the note
from `vsim/bin/run.makefile`).
---- Updated some other minor issues which is not matter much, please check the
git history if you really care to.
---- Note: This version does not support the hardware-breakpoint yet, i.e.,
you cannot set the breakpoint to read-only address space (e.g., ROM, Flash).
But soft-break is okay, means you can use regular interactive debugger
functionalities (including set breakpoint to the regular R/W address space).
-- The earlier-test version uploaded to github to try.
-- NOTE:
---- This is not the official release, please wait the official release which will coming
soon and will be recorded at here. You will see the Release History updates.