automatic register inteface RTL generator with better excel template
Compared with other similar tools:
- with pretty excel template with good readability
- with safety validation check, never generate broken verilog
- with pretty and clear verilog code style
- develop with python, cross platform[windows, linux, macos]
- full feature(clock-gate/read-group/reset-macro/mem/fifo/)
- open source, docx, json, cHead will be supported
pip install regif
you can also directly use python regif.py mymodule.xls
step1: regif --init mymodule will generate mymodule.xls template at current dir,
step2: then you need specify your owner register in mymodule.xls
step3: regif mymodule.xls generate my_ip.v[my_ip_wrap.v], my_ip.docx at current dir
RO
WO
RW
RC
WC
CP
BP
RWT
RWP
W1S
W1C
- interruption
- configure lockable
- trigger or start
- read-group
- fifo
- mem
- clockgate
- reset macro
- xx
- xx