BishengJDK 11 now brings the template interpreter and backends of C1/C2 compiler to the RISC-V world. We supports RV64G (G used to be represent the IMAFD base and extensions of RISC-V ISA) with BV (bit-manipulation and vector extensions) on the way, and the compressed instructions are out of plan.
Please refer to the building suggestions.
BishengJDK follows GPLv2 with Classpath Exception，see License。
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Features:
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We almost cover all components of jdk11, except AOT/Graal and Shenandoah GC. The Shenandoah GC will comming soon in the near future, and AOT and Graal is depending. Note that the OpenJDK community has disabled the features in Oracle builds in JDK16.
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B/V extensions
- The both two extensions of ISA are currently draft versions and not released yet. V is close to stable, and so we will introduces the vector instructions to the C2 backends and intrinsics soon.
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Intrinsics
- Lots of intrinsics depends on the B extension and will be dedicate if wrote by the B/V instructions, and other intrinsics of few methods of String and Arrays are now available.
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Considerations:
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Frame layout
- Java frames are organized as other platforms, following the fp links, but native frames are arranged as the riscv style, of which the fp pointing to the sender sp.
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Cross-modifying code
- We believe that the same story happened on the riscv machines. Details of the issue see https://bugs.openjdk.java.net/browse/JDK-8223613. We followed the conservative solution as same as the Aarch64 port, deoptimization when patching in C1. And the rest of risky may be addressed by the invoke bindings JEP.
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Comparing to other architecutures, more efforts were paid in the code genaration for addressing the short offset of branch instructions, the no-flag-register architecture, the simplest addressing mode and so on.
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Tests
- We have passed 17000+ jtreg test cases, cross-compiled on x86 machines and ran on the user mode of QEMU RISCV64. And we hope to promote more tests and benchmarks on the real riscv machine in the future if possible.