felixhsu123

0x55AA

Group Assignments for a University Class

2-Stage-CNN-Accelerator

A two-staged CNN hardware accelerator using Verilog RTL for machine learning applications.

ACF_GPU

GPU version of ACF pedestrian detection

ACFPedestrianDetection

基于ACF行人检测框架，引入EdgeBox特征和Salient特征，使用real adaboost算法，显著提高行人检测算法的准确率和泛化能力。

AgeGenderDeepLearning

FishEyeRepair

鱼眼变换算法研究

Lane-Detection

Lane departure warning system is a mechanism designed to warn a driver when the vehicle begins to move out of its lane (unless a turn signal is on in that direction) on freeways. The system is designed to minimize accidents by addressing the main causes of collisions: driver error, distractions and drowsiness. The aim of this project is to implement the core algorithm of this feature which is the lane detection. The aim is to detect road lane markers in a video stream and to highlight the lane in which the vehicle is driven by detecting boundaries of the lane markers in the video.

mlnd_distracted_driver_detection

基于深度学习的驾驶员状态检测，不仅仅可以识别出疲劳驾驶，还能够识别出各种各样的状态

opencv-

运用球面平面映射，解决畸变矫正

felixhsu123/AntiGrainGeometry-v2.4

a 1:1 backup copy of Anti-Grain Geometry v2.4

felixhsu123/arm-isp

felixhsu123/arm-isp-dirver

felixhsu123/biorealistic-spiking-neural-network

Implements Izhikevich Neuron which spikes at rates close to a biological neural network based on the IEEE paper

felixhsu123/block-nvdla-sifive

felixhsu123/booth-multiplier

felixhsu123/bru-firesim

BRU: Bandwidth Regulation Unit for Real-Time Multicore Processors

felixhsu123/c910-llvm

平头哥玄铁C910的LLVM工具链支持，由PLCT实验室提供，非官方版本

felixhsu123/CHaiDNN

HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs

felixhsu123/cnn_hardware_acclerator_for_fpga

This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Networks on FPGAs

felixhsu123/CycleISP

Official repository for "CycleISP: Real Image Restoration via Improved Data Synthesis" (CVPR 2020--Oral)

felixhsu123/doc

Documentation for NVDLA.

felixhsu123/EndoscopySmokeRemoval

A small but interesting research on medical endoscope

felixhsu123/ESP32

L3：Espressif Xtensa LX6 BT&WiFi SoC（ESP32）

felixhsu123/ESP8266

L2：espressif 160MHz MIPS Tensilica L106 WiFi SoC (ESP8266/ESP8285)

felixhsu123/firesim-nvdla

FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud

felixhsu123/Hardware-acceleration-for-FFT-IFFT-algorithm

FFT/IFFT algorithm acceleration from the hardware perspective. Apply TIE (Tensilica Instruction Extension) to configure the processor Xtensa developed by company Tensilica.

felixhsu123/High-Performance-ALU

RTL Design and Implementation of High Performance Algorithm Logic Units

felixhsu123/High-Performance-DSP

RTL system design and implementation for high-performance FIR/IIR filters

felixhsu123/hisi3559sample

felixhsu123/hw

RTL, Cmodel, and testbench for NVDLA

felixhsu123/iSmartDNN

Light-weighted neural network inference for object detection on small-scale FPGA board

felixhsu123/isp_for_armv2__20190428

felixhsu123/MLP-FeedForward-RTL-Acceleration

Register Transfer Level Acceleration of FeedForward Propagation in 2-Layer Perceptron Networks (My B.Sc. Thesis, Phase 3/3)

felixhsu123/mnist-digit-recognition-cortex-m4

ARM Cortex-M4 based inference engine to classify handwritten digits

felixhsu123/Neural-Network-Acceleration-2

Neural Network Acceleration using CPU/GPU, ASIC, FPGA

felixhsu123/neural-network-optimization

Neural Network Optimization Flow for efficient hardware inference

felixhsu123/RDA5981

L2：cortex M4 160MHz WiFi SoC（RAD5981）

felixhsu123/sw

NVDLA SW

felixhsu123/wujian100_open

IC design and development should be faster，simpler and more reliable