- Some simple verilog practice
- Implement a 4x2 priority encoder
- Implement a Full Adder
- Implement a 5 bits ripple adder with hierarchy skills
- Implement a 8 to 1 mux
- A simple ALU instruction set
- A simple grayscale module using shift to map 24 bits r,g,b color into 8 bits The result is approximation due to loss of shift operation
- A simple model for a 64*32 register file
- A simple model for a vending machine which can do:
Get input money
Get price of selected beverage
Output the change = money - price
- A simple 3*3 convolution model with shift reg
- A simple moore FSM
- A simple mealy FSM
- A simple 65536*24bits RAM module
- A simple 16384*24bits ROM module
- A simple shift convolution module
- A simple grayscale converter which convert 800*600 bmp rgb pics into gray scale pic