/FPGA-Synthesizable-Verilog-Modules

Primary LanguageVerilog

FPGA Synthesizable Verilog Modules

Overview

This repository contains a collection of Verilog modules that are synthesizable on FPGA. The modules are derived from detailed examples and guidelines discussed in the "Computer aided Digital System Design" course.

Contents

The repository includes Verilog files for the following modules:

  • Adders (Full, Half, etc.)
  • Shift Registers (Shift Left, Shift Right, Dynamic Shift, etc.)
  • Counters (Up, Down, Up/Down, etc.)
  • Multiplexers and Decoders
  • Finite State Machines (FSM)
  • Memory Elements (RAM, ROM)
  • Arithmetic Units (Multipliers, Accumulators)
  • And many others

Each module is provided as a .v file that can be directly used or modified for your specific requirements.

Usage

To use these modules, clone this repository and import the desired Verilog files into your design tool. These modules are written in a way that they can be synthesized on various FPGA platforms.

git clone https://github.com/fereshtehbaradaran/FPGA-Synthesizable-Verilog-Modules