XBox 360: Front Side Bus
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Referring to this section: https://www.copetti.org/writings/consoles/xbox-360/#memory-controller
With all being said, how can Xenon access this memory? Well, the CPU communicates with the GPU through an interface called Front-side Bus that uses two unidirectional buses, the ‘CPU→GPU’ lane is 64 bits wide and runs at 1.35 GHz, while the ‘GPU→CPU’ one is 128-bits wide and runs at 675 MHz [21]. If we do the math, both lanes provide a bandwidth of 10.8 GB/s.
In the image it doesn't look at all like a super-wide interface; it looks like a bunch of differential pairs. Digging into the cited source, it makes a somewhat different claim:
The FSB [...] physical layer has 10.8GB/sec bandwidth, a target specified to support procedural geometry. On the CPU side, this interfaces to a 1.35GHz, 8B wide, FSB dataflow; on the GPU side, it connects to a 16B wide FSB dataflow running at 675Mhz.
The different interfaces (64 bits wide and 128 bits wide, respectively) seem to refer to the internal busses of the CPU and GPU chip that interface with the FSB unit. This is clarified a bit later:
The physical layer (PHY) itself is structured as two unidirectional links, each link consisting of two single-byte lanes, with one clock each. The links are source-synchronous, so the receive clock is sent with the data. The clocks run at 5.4GHz, and each link delivers 10.8 GB/sec bandwidth.
I.e. the FSB consists of two symmetric, unidirectional CML links, each 16 bit wide, running at 5.4 GHz. This is also matches the image from the article, as you can see there are a bunch of differential pairs running between these pairs. I counted 24 pairs on the top and 16 on the bottom layer (https://www.edn.com/wp-content/uploads/media-1128294-267511-pry-360elite-20099.jpg), for a total of 40 pairs. There is a paper (https://ieeexplore.ieee.org/document/4196141) which describes the FSB in detail. That paper explains that each byte-lane also has a 9th bit called "flag" which is used for packet framing, and a separate clock. This gives 40 differential pairs for the entire FSB (2x [directions] 2x [lanes] x (8 [bits] + 1 [flag] + 1 [clock])).
Fig 1. from that paper also corroborates source [21]. The paper also mentions that the XBox 360 mainboard is made from an "ultra low cost" [so probably regular FR4] 2s2p [two signal and two power layers] PCB though that's probably not news.
Thanks for flagging this, I've amended that paragraph. What do you think of the changes?
Feel free to open this issue again if you spot any mistakes in the corrections.