computer-architecture
There are 1631 repositories under computer-architecture topic.
Developer-Y/cs-video-courses
List of Computer Science courses with video lectures.
MattPD/cpplinks
A categorized list of C++ resources.
mortbopet/Ripes
A graphical processor simulator and assembly editor for the RISC-V ISA
Exely/CSAPP-Labs
Solutions and Notes for Labs of Computer Systems: A Programmer's Perspective 3rd Editon // 《深入理解计算机系统》第三版的实验文件、解答与笔记
baquer/GATE-and-CSE-Resources-for-Students
📚 📖 📚CSE GATE Resources for GATE and CSE Aspirants 😎 😁 . Show your ❤️ by ⭐️⭐️
o-oconnell/minixfromscratch
Development and compilation setup for the book versions of MINIX (2.0.0 and 3.1.0) on QEMU
flipacholas/Architecture-of-consoles
Technical articles about console architecture
sam-astro/Astro8-Computer
Custom 16-bit homebrew CPU, emulator, renderer, PCB, and language
jsdf/little-virtual-computer
Learn how computers work by simulating them in Javascript
ChampSim/ChampSim
ChampSim is an open-source trace based simulator maintained at Texas A&M University and through the support of the computer architecture community.
jobhope/TechnicalNote
Repository to store what we have studied. :book: We want everyone to get a job through TechnicalNote.
mikeroyal/RISC-V-Guide
RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.
cvut/qtrvsim
RISC-V CPU simulator for education purposes
kangtegong/self-learning-cs
『혼자 공부하는 컴퓨터구조 & 운영체제』 (한빛미디어)
rajesh-s/computer-architecture-and-systems-resources
A curated list of Computer Architecture and Systems resources
zhangyachen/ComputerArchitectureAndCppBooks
📚 计算机体系结构与C++书籍收集(持续更新)
MIPT-ILab/mipt-mips
Cycle-accurate pre-silicon simulator of RISC-V and MIPS CPUs
rsms/rsm
Virtual computer
umd-memsys/DRAMSim2
DRAMSim2: A cycle accurate DRAM simulator
JackonYang/paper-reading
比做算法的懂工程落地，比做工程的懂算法模型。
kangtegong/csnote
컴퓨터 과학 키워드 총정리 / computer science keyword notes
sudonam/open-college-courses
open-college-courses
mathis-s/SoomRV
A simple superscalar out-of-order RISC-V microprocessor
paulveillard/cybersecurity
Welcome Cybersecurity's World. An ongoing & curated collection of awesome software best practices and techniques, libraries and frameworks, E-books and videos, websites, blog posts, links to github Repositories, technical guidelines and important resources in Cybersecurity.
skyzh/RISCV-Simulator
💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visualization. Project report available.
sarchlab/mgpusim
A highly-flexible GPU simulator for AMD GPUs.
hao-lh/the-books-making-you-better
This repo is a curated library to help you achieve a deeper understanding of what drives success and continuous improvement. Dive in, and discover content that can expand your thinking, sharpen your expertise, and fuel you drive better, whether you’re exploring new fields, honing in-demand skills, or simply looking for fresh perspectives.
err0r500/foundational-knowledge-for-programmers
List of resources about foundational knowledge for programmers (supposed to last a few decades)
mhyousefi/MIPS-pipeline-processor
A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding
Mariotti94/WebRISC-V
WebRISC-V: A Web-Based Education-Oriented RISC-V Pipeline Simulation Environment [PHP]
Maecenas/ICS-15213-CSAPP3e-CMU
:mortar_board::whale: Dev Environment and Lab Assignments of the Introduction to Computer Systems course, CMU 15-213, 2015 Fall
KASIRGA-KIZIL/tekno-kizil
KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi
CMU-SAFARI/Pythia
A customizable hardware prefetching framework using online reinforcement learning as described in the MICRO 2021 paper by Bera et al. (https://arxiv.org/pdf/2109.12021.pdf).
ILLIXR/ILLIXR
ILLIXR: Illinois Extended Reality Testbed
ash-olakangal/RISC-V-Processor
Verilog implementation of multi-stage 32-bit RISC-V processor
neelkshah/MIPS-Processor
5-stage pipelined 32-bit MIPS microprocessor in Verilog