/RISCV-Simulator

💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visualization. Project report available.

Primary LanguageC++MIT LicenseMIT

RISCV-Simulator

Build Status

RISCV-Simulator implemented in C++. Support RV32I ISA.

Generally this should be done with a 5-stage pipeline. This implementation may be found at pipeline branch.

All CPU and CPU simulators I've made are listed below.

Technique Implementation
RISC-V v1 5-stage pipeline simulator C++
RISC-V v2 dynamic scheduling simulator
Tomasulo + Speculation		 C++
MIPS 5-stage pipeline simulator Haskell
MIPS 5-stage pipeline CPU Verilog

The architecture is derived from Tomasulo and Speculation described in CA:AQA Chapter 3. While the method in the textbook is not detailed enough to carry out a CPU design (It illustrates the algorithm with only one float unit instead of a CPU), I came up with some ideas to complete the design for a fully-functional RISC-V CPU. It can be summarized as follows:

  • Handle memory hazards
  • RISC-V jalr instruction
  • Handle branch mis-prediction in the architecture with just Tomasulo algorithm

For a full report on how I made this simulator and solutions to the challenges above, refer to Make You a RISC-V Simulator (PDF, Chinese)

For statistics and reports on sample programs, refer to Travis-CI build log.

This branch simulates a RISC-V CPU of 2 stage: issue and execute, which supports out-of-order execution.

It implements out-of-order execution with Tomasulo algorithm. For branch, It applies hardware speculation to speculate the following instructions. 3 load buffer, 3 store buffer, 4 ALU unit, and a 12-entry reorder buffer. Use Two-level adaptive predictor for branch prediction.

Note that since I was unable to design the equivalent circuit, this branch just shows a programmer's way to illustrate out-of-order execution design.

You may go into Presentation Mode to view detailed execution information.

Screen Shot 2019-09-06 at 10 07 22 AM

Branch Build Status Note
seq Build Status A sequential implementation. First edition. No feed forward.
feedforward Build Status Second edition. Based on seq. Feeding forward runs faster. (Though I don't like it.)
pipeline Build Status Pipelined version. Based on seq. Handle hazard by forwarding. Two-level adaptive predictor.
out-of-order Build Status Out-of-order execution with Tomasulo algorithm and Speculation.
master Build Status For online judge