foallan

Pinned Repositories

2D-Binary-Content-Addressable-Memory-BCAM
Modular SRAM-based 2D hierarchical-search Binary Content Addressable Memory (2D-BCAM)
Language:Verilog00
Binary-to-BCD-Converter
Parametric Binary to BCD Converter Using Double Dabble / Shift and Add 3 Algorithm
Language:Verilog00
Cell-Based-Layout-Compaction
Cell-based VLSI layout compaction algorithm based on a modified Segments tree data structure; programmed in Perl script
Language:Perl0 0 00
Cell-Based_Mixed-Timing_FIFO.Synopsys_Flow
This package includes a complete design framework based on Synopsys tools for mixed asp* asynchronous and clocked synchronous cell-based FIFOs
Language:Verilog0 1 00
cell-based_mixed_fifo.flow
This package includes a complete design framework for mixed asp* asynchronous and clocked synchronous cell-based FIFOs
Language:Verilog00
Dynamic-Frequency-Phase-Sweeping
Dynamic Run-time Frequency and Phase Sweeping for Altera's PLLs with Freq. and Phase Meters
Language:Verilog00
Indirectly-Indexed-2D-Binary-Content-Addressable-Memory-BCAM
Modular SRAM-based indirectly-indexed 2D hierarchical-search Binary Content Addressable Memory (II-2D-BCAM)
Language:Verilog0 0 00
Indirectly-Indexed-2D-Ternary-Content-Addressable-Memory-TCAM
Modular SRAM-based indirectly-indexed 2D hierarchical-search Ternary Content Addressable Memory (II-2D-TCAM)
Language:Verilog0 0 00
Interleaved-Synthesizable-Synchronization-FIFOs
Interleaved Architectures for High-Throughput Synthesizable Synchronization FIFOs
Language:Verilog0 0 00
LUT-Input-Permutations-Enumerator
LUT-Input-Permutations-Enumerator; A permutations enumerator circuit based on Lehmer's code; synthesis and verification frameworks are provided
Language:SystemVerilog00

foallan's Repositories

foallan/2D-Binary-Content-Addressable-Memory-BCAM
Modular SRAM-based 2D hierarchical-search Binary Content Addressable Memory (2D-BCAM)
Language:Verilog00
foallan/Binary-to-BCD-Converter
Parametric Binary to BCD Converter Using Double Dabble / Shift and Add 3 Algorithm
Language:Verilog00
foallan/Cell-Based-Layout-Compaction
Cell-based VLSI layout compaction algorithm based on a modified Segments tree data structure; programmed in Perl script
Language:Perl0 0 00
foallan/Cell-Based_Mixed-Timing_FIFO.Synopsys_Flow
This package includes a complete design framework based on Synopsys tools for mixed asp* asynchronous and clocked synchronous cell-based FIFOs
Language:Verilog0 1 00
foallan/cell-based_mixed_fifo.flow
This package includes a complete design framework for mixed asp* asynchronous and clocked synchronous cell-based FIFOs
Language:Verilog00
foallan/Dynamic-Frequency-Phase-Sweeping
Dynamic Run-time Frequency and Phase Sweeping for Altera's PLLs with Freq. and Phase Meters
Language:Verilog00
foallan/Indirectly-Indexed-2D-Binary-Content-Addressable-Memory-BCAM
Modular SRAM-based indirectly-indexed 2D hierarchical-search Binary Content Addressable Memory (II-2D-BCAM)
Language:Verilog0 0 00
foallan/Indirectly-Indexed-2D-Ternary-Content-Addressable-Memory-TCAM
Modular SRAM-based indirectly-indexed 2D hierarchical-search Ternary Content Addressable Memory (II-2D-TCAM)
Language:Verilog0 0 00
foallan/Interleaved-Synthesizable-Synchronization-FIFOs
Interleaved Architectures for High-Throughput Synthesizable Synchronization FIFOs
Language:Verilog0 0 00
foallan/LUT-Input-Permutations-Enumerator
LUT-Input-Permutations-Enumerator; A permutations enumerator circuit based on Lehmer's code; synthesis and verification frameworks are provided
Language:SystemVerilog00
foallan/Multi-Fanout-Kernighan-Lin-Hypergraph-Bi-Partitioning
An enhanced version of the Kernighan-Lin based bi-partitioning algorithm for circuits with multi-fanout nets.
Language:C
foallan/Multi-Sink-Lee-Moore-Shortest-Path-Maze-Router
This is an implemention of Lee-Moore's Shortest Path Maze Router with multi-sink nets support.
Language:C0 0
foallan/Multiported-RAM
Modular Multi-ported SRAM-based Memory
Language:Verilog
foallan/Multiported-RAM-Compiler
A Multi-Ported Memory Compiler Utilizing True Dual-Ported BRAMs
Language:C0 0
foallan/Polygonal-Layout-Layer-Arithmetics
Algorithmic VLSI layout layer arithmetic operations based on a modified Segments tree data structure for finding the contour of union of rectangles; programmed in Perl script
Language:Perl
foallan/Simulated-Annealing-Cell-Based-Placer
This is an implemention of a simulated-annealing standard-cell placement tool; The tool assigns physical locations to each cell in a circuit.
Language:C
foallan/Switched-Multiported-RAM
Switched SRAM-based Multi-ported RAM
Language:Verilog
foallan/Timing-Driven-Variation-Aware-Clock-Mesh-Synthesis
Timing-Driven Variation-Aware Clock Mesh Synthesis Environment; programmed in Perl and TCL scripts
Language:Verilog
foallan/Verilog-Quartus-Mapping-VQM-Netlist-Parser
generates a Comma-Separated Values (CSV) file of all nodes in a given Verilog Quartus Mapping (VQM) netlist and their respective fanouts, ordered by fanout (highest first)
Language:Verilog0 0