/zcu102-ethernet

Design for using Ethernet on the ZCU102 development board

Primary LanguageTclMIT LicenseMIT

zcu102-ethernet

Example design for using Ethernet on the ZCU102 board via it's RJ45 connector and SFP ports.

Requirements

This project is designed for version 2019.2 of the Xilinx tools (Vivado/SDK/PetaLinux). If you are using an older version of the Xilinx tools, then refer to the release tags to find the version of this repository that matches your version of the tools.

Build instructions

To use the sources in this repository, please follow these steps:

Windows users

  1. Download the repo as a zip file and extract the files to a directory on your hard drive --OR-- Git users: clone the repo to your hard drive
  2. Open Windows Explorer, browse to the repo files on your hard drive.
  3. In the Vivado directory, you will find multiple batch files (*.bat). Double click on the batch file that is appropriate to your hardware, for example, double-click build-zcu102.bat if you are using the ZCU102. This will generate a Vivado project for your hardware platform.
  4. Run Vivado and open the project that was just created.
  5. Click Generate bitstream.
  6. When the bitstream is successfully generated, select File->Export->Export Hardware. In the window that opens, tick "Include bitstream" and "Local to project".
  7. Return to Windows Explorer and browse to the SDK directory in the repo.
  8. Double click the build-sdk.bat batch file. The batch file will run the build-sdk.tcl script and build the SDK workspace containing the hardware design and the software application.
  9. Run Xilinx SDK (DO NOT use the Launch SDK option from Vivado) and select the workspace to be the SDK directory of the repo.
  10. Select Project->Build automatically.
  11. Connect and power up the hardware.
  12. Open a Putty terminal to view the UART output.
  13. In the SDK, select Xilinx Tools->Program FPGA.
  14. Right-click on the application and select Run As->Launch on Hardware (System Debugger)

Linux users

  1. Download the repo as a zip file and extract the files to a directory on your hard drive --OR-- Git users: clone the repo to your hard drive
  2. Launch the Vivado GUI.
  3. Open the Tcl console from the Vivado welcome page. In the console, cd to the repo files on your hard drive and into the Vivado subdirectory. For example: cd /media/projects/ethernet-fmc-zynq-gem/Vivado.
  4. In the Vivado subdirectory, you will find multiple Tcl files. To list them, type exec ls {*}[glob *.tcl]. Determine the Tcl script for the example project that you would like to generate (for example: build-zcu104.tcl), then source the script in the Tcl console: For example: source build-zcu102.tcl
  5. Vivado will run the script and generate the project. When it's finished, click Generate bitstream.
  6. When the bitstream is successfully generated, select File->Export->Export Hardware. In the window that opens, tick "Include bitstream" and "Local to project".
  7. To build the SDK workspace, open a Linux command terminal and cd to the SDK directory in the repo.
  8. The SDK directory contains the build-sdk.tcl script that will build the SDK workspace containing the hardware design and the software application. Run the build script by typing the following command: <path-of-xilinx-sdk>/bin/xsdk -batch -source build-sdk.tcl. Note that you must replace <path-of-xilinx-sdk> with the actual path to your Xilinx SDK installation.
  9. Run Xilinx SDK (DO NOT use the Launch SDK option from Vivado) and select the workspace to be the SDK subdirectory of the repo.
  10. Select Project->Build automatically.
  11. Connect and power up the hardware.
  12. Open a Putty terminal to view the UART output.
  13. In the SDK, select Xilinx Tools->Program FPGA.
  14. Right-click on the application and select Run As->Launch on Hardware (System Debugger)

Stand-alone software application

The software application used to test these projects is the lwIP Echo Server example that is built into Xilinx SDK.

Port Connections

The RJ45 connector is connected to GEM3 via the MIO interface.

The SFP cages are connected to the GTH transceivers and AXI Ethernet IPs as follows:

  • Right-top cage, GTH X1Y12, axi_ethernet_0
  • Right-lower cage, GTH X1Y13, axi_ethernet_1 (not yet implemented)
  • Left-top cage, GTH X1Y14, axi_ethernet_2 (not yet implemented)
  • Left-lower cage, GTH X1Y15, axi_ethernet_3 (not yet implemented)

About us

This project was developed by Opsero Inc., a tight-knit team of FPGA experts delivering FPGA products and design services to start-ups and tech companies. Follow our blog, FPGA Developer, for news, tutorials and updates on the awesome projects we work on.