freechipsproject/firrtl-interpreter

Issues

• Wire assignment to output of Reg does not always work

  #137 opened 9 months ago by nullromo
  7

• libraryDependencies issue

  #220 opened 3 years ago by AltiumHanChou
  2

• Peek on internal Vec or elements of Seq?

  #43 opened 8 years ago by shunshou
  9

• Interpreter's reset behavior does not match verilator backend.

  #118 opened 7 years ago by chick
  2

• Simulation with BlackBoxImplementation fails

  #112 opened 5 years ago by sommerlukas
  10

• Negative SInt values show up as Xs in VCD output, other discrepancies between firrtl and verilator VCD traces

  #109 opened 5 years ago by rimasaviz
  2

• Convert to using new Logger

  #50 opened 5 years ago by chick
  1

• vcd needs to be cleaned up

  #35 opened 5 years ago by chick
  1

• make interpreter up to date with blackbox parameterization

  #34 opened 5 years ago by chick
  1

• Ivalid Clock interpretation

  #138 opened 5 years ago by tampler
  7

• firrtl-interpreter internal structure

  #148 opened 6 years ago by kai413629305
  2

• Chirrtl Reference not declared for Mutable Map

  #144 opened 6 years ago by tampler
  8

• Bug in handling and() PrimOp with sign extension

  #145 opened 6 years ago by chick
  0

• How to silence log output during `evaluateCircuit`

  #141 opened 6 years ago by nhynes
  0

• Verilog BlackBox clocking, the right way

  #136 opened 6 years ago by tampler
  2

• FIR crashes during the ByteBuffer conversion

  #135 opened 6 years ago by tampler
  4

• Incorrect `not` behavior

  #122 opened 6 years ago by seldridge
  7

• "exception Expression key dcache.wen already in stack" when loading riscv-mini's Tile.fir

  #127 opened 7 years ago by taomiao
  1

• Interpreter should do stronger tests for legal input values

  #116 opened 7 years ago by chick
  0

• Init behavior between interpreter and verilator simulations is different.

  #110 opened 7 years ago by chick
  1

• Firrtl interpreter should support wider wires

  #26 opened 7 years ago by chick
  1

• After freechipsproject/firrtl#706, interpreter tests fail

  #106 opened 7 years ago by ucbjrl
  7

• Lowering pass generates Firrtl with memory's clock connected to validIf

  #105 opened 7 years ago by chick
  1

• Be able to use a .vcd file as an input script.

  #45 opened 7 years ago by chick
  1

• Black boxes with no implementations are silently ignored

  #68 opened 7 years ago by chick
  0

• BlackBox implementations do not support black boxes with more than one output

  #84 opened 7 years ago by chick
  9

• Interpreter builds modules twice

  #86 opened 7 years ago by stevenmburns
  7

• Tester produces wrong results as parameterized testcase grows in size

  #28 opened 8 years ago by stevenmburns
  4

• Nobody expects the CombLoopException

  #78 opened 8 years ago by ucbjrl
  0

• InterpretiveTester construction takes a long time

  #71 opened 8 years ago by stevenmburns
  7

• Better instrumentation and rendering of that instrumentation

  #17 opened 8 years ago by chick
  0

• Error happens when initializing registers

  #37 opened 8 years ago by pingfanm
  5

• Support needed for black boxes

  #16 opened 8 years ago by chick
  3

• Mux condition width change

  #15 opened 8 years ago by ucbjrl
  1

• DynamicMemorySearch test failing

  #19 opened 8 years ago by chick
  0

• Runtime assert (or stop) should raise an exception

  #30 opened 8 years ago by stevenmburns
  3

• Build is broken

  #55 opened 8 years ago by grebe
  2

• Width errors should not occur during interpreter load

  #46 opened 8 years ago by chick
  1

• Error happens assigning to SInt from bits()

  #13 opened 8 years ago by chick
  2

• Bad Error Message when exceeding width

  #39 opened 8 years ago by sagark
  2

• Concrete.randomSInt produces illegal value

  #18 opened 8 years ago by chick
  1

• Default values for uninitialized concrete values should be randomized

  #9 opened 8 years ago by chick
  1

• Negative SInts can generate error with: and, or, xor operations

  #23 opened 8 years ago by chick
  1

• Request ability to poke not just the interface but also the internal state registers

  #22 opened 8 years ago by stevenmburns
  4

• Consider using concrete values for indices to memory

  #11 opened 8 years ago by chick
  0