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This repository is clone of original riscv-gcc modified for handling floating point exceptions. Changes were made in riscv.md.
Following floating point operations generate breakpoints when any floating point exception occurs:
- multiplication
- addition
- substraction
- division
riscv.md is used to generate assembly instructions from RTL. It contains machine description consisting of rules for instruction selection and register allocation, pipeline description, and peephole optimizations.
Assembly instructions corresponding to following RTL instruction patterns correspoding to above listed has been changed:
fmulfaddfdivfsub
Assembly instructions added for fmul : `
frcsr\ta3
beqz\ta3, 1f
ebreak
1:frcsr is used to read the content on Floating point Control and Status Register(FPCSR). Corresponding bit in FPCSR gets set when any floating point exception occurs. Branching occurs if no FPCSR is zero, skippinf the ebreak instruction which is responsible for generating breaking point.
Local labels are denoted by numbers. Here 1 is used for fmul instruction pattern.
Programs to demonstrate various floating point exceptions are inside examples directory. After generating executable, Spike simulator is required to run it.
This is a work in progress. Next steps should make following changes:
- Changning register a3 to any arbitary register.
- Option to enable or disable the change
- Better method should be used to exit from program
- More helpful error message should be displayed
- Option to enable or disable different floating point exception