Pinned Repositories
100DaysOfRTL
I was inspired by @raulbehl challenge to code a module everyday and progressively improve on coding skills. So here I am giving it a shot!
6th-Sem
ngl I do give some credits to chatGPT XD
AF_Website
APB_Protocol
irony I tried to learn the logic of APB bus, before googling it's full form its Advanced Peripheral Bus guys! :p
azadi-soc
Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.
caravel_cocotb
RISC-V-CPU-Core
This repo contains the codes which I implemented while completing the course "Building a RISC-V CPU Core" offered by Linux Foundation through edx.
Term-Project
VLSI_Mini_Project
Implementation of Verilog Integrator using Lorentz Equations using Nexys 4 DDR FPGA Developement Kit.
VLSI_design-of-RISC
IEEE Executive project for the year 2021-2022
gagana-05's Repositories
gagana-05/100DaysOfRTL
I was inspired by @raulbehl challenge to code a module everyday and progressively improve on coding skills. So here I am giving it a shot!
gagana-05/APB_Protocol
irony I tried to learn the logic of APB bus, before googling it's full form its Advanced Peripheral Bus guys! :p
gagana-05/azadi-soc
Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.
gagana-05/RISC-V-CPU-Core
This repo contains the codes which I implemented while completing the course "Building a RISC-V CPU Core" offered by Linux Foundation through edx.
gagana-05/VLSI_Mini_Project
Implementation of Verilog Integrator using Lorentz Equations using Nexys 4 DDR FPGA Developement Kit.
gagana-05/6th-Sem
ngl I do give some credits to chatGPT XD
gagana-05/AF_Website
gagana-05/axi_dma
General Purpose AXI Direct Memory Access
gagana-05/caravel_cocotb
gagana-05/Term-Project
gagana-05/caravel-sim-infrastructure
gagana-05/Caravel_cocotb_verification_tutorial
gagana-05/caravel_setup
gagana-05/cvw
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
gagana-05/Floating-Point-ALU-in-Verilog
32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
gagana-05/FPGA_basics
gagana-05/gagana-05
Config files for my GitHub profile.
gagana-05/gagana-05.github.io
gagana-05/i2c
I2C controller core
gagana-05/impulse_workshop
gagana-05/ODE_solver
VLSI Mini Project
gagana-05/picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
gagana-05/pulpissimo-ptf
This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
gagana-05/RISC-V-SoC
SoC project
gagana-05/runs_caravel
Adding some simple runs here
gagana-05/SerialAdder
Parameterized Serial Adder
gagana-05/sram
gagana-05/vga-playground
Playground for VGA projects on Tiny Tapeout
gagana-05/VLSI-Lab-2022
gagana-05/x-heep
eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V