Pinned Repositories
amiq_apb
SystemVerilog VIP for AMBA APB protocol
amiq_eth
Library defining all Ethernet packets in SystemVerilog and in SystemC
arrayfire
ArrayFire: a general purpose GPU library.
ASIC_Design_and_CUDA
awesome-machine-learning
A curated list of awesome Machine Learning frameworks, libraries and software.
cores
Various HDL (Verilog) IP Cores
cuda-samples
Samples for CUDA Developers which demonstrates features in CUDA Toolkit
gpgpu-papers
Ye Olde GPGPU Scrolls.
ModernSystemC
Example code for Modern SystemC using Modern C++
SuperScalar-RISCV-CPU
SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
ganesh-rahate's Repositories
ganesh-rahate/arrayfire
ArrayFire: a general purpose GPU library.
ganesh-rahate/awesome-machine-learning
A curated list of awesome Machine Learning frameworks, libraries and software.
ganesh-rahate/ModernSystemC
Example code for Modern SystemC using Modern C++
ganesh-rahate/axi
AXI4 and AXI4-Lite synthesizable modules and verification infrastructure
ganesh-rahate/AXI4
AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
ganesh-rahate/bsg_manycore
Tile based architecture designed for computing efficiency, scalability and generality
ganesh-rahate/C-Cpp-Notes
Notes about modern C++, C++11, C++14 and C++17, Boost Libraries, ABI, foreign function interface and reference cards.
ganesh-rahate/common_cells
Common SV components
ganesh-rahate/corundum
Open source, high performance, FPGA-based NIC
ganesh-rahate/cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
ganesh-rahate/darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
ganesh-rahate/dpi-models
ganesh-rahate/fpnew
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
ganesh-rahate/GPCore
This is the base repo for our graduation project in AlexU 21
ganesh-rahate/gpgpu-sim_distribution
GPGPU-Sim provides a detailed simulation model of contemporary NVIDIA GPUs running CUDA and/or OpenCL workloads. It includes support for features such as TensorCores and CUDA Dynamic Parallelism as well as a performance visualization tool, AerialVisoin, and an integrated energy model, GPUWattch.
ganesh-rahate/gpu_programming_intro
ganesh-rahate/modern-cpp-tutorial
📚 Modern C++ Tutorial: C++11/14/17/20 On the Fly
ganesh-rahate/NyuziProcessor
GPGPU microprocessor architecture
ganesh-rahate/openofdm
Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.
ganesh-rahate/pulpissimo
This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
ganesh-rahate/qemu
Official QEMU mirror. Please see http://wiki.qemu.org/Contribute/SubmitAPatch for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.
ganesh-rahate/riscv-boom
SonicBOOM: The Berkeley Out-of-Order Machine
ganesh-rahate/riscv-cores-list
RISC-V Cores, SoC platforms and SoCs
ganesh-rahate/riscv-dv
SV/UVM based instruction generator for RISC-V processor verification
ganesh-rahate/systemctlm-cosim-demo
ganesh-rahate/UVVM
UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/
ganesh-rahate/UVVM_SUPPLEMENTARY
ganesh-rahate/verilog-axi
Verilog AXI components for FPGA implementation
ganesh-rahate/warp-v
WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
ganesh-rahate/wb2axip
Bus bridges and other odds and ends