The python program takes a configuration file describing a State Machine and genertes a source file and a verilog testbench file for the same.
Check out a sample input state machine file at sm.conf
Check a sample input test file @ test.in
Verilog Source File Generation — To generate the source file module is the name of the module as well as the generated verilog file
./main.py -s sm_conf -m module_name
Compile Using IVerilog — To compile the verilog file using icarus verilog
Modify the testbench file tb.v to update the module DUT name, the file name where to read the input stimulus data and the file name where to store the generated output
iverilog -o output module.v tb.v
vvp output
View the waveform — To view the waveform in gtkwave
By default the waveform data is dumped in test.vcd file in test folder. Modify the tb.v file for any specifics
gtkwave test/test.vcd