gdessouky

Google | OpenTitan TeamMunich, Germany

Pinned Repositories

cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
Language:SystemVerilog0 0 00
hackdac_2018_beta
The SoC used for the beta phase of Hack@DAC 2018.
Language:SystemVerilog6 1 00
opentitan
OpenTitan: Open source silicon root of trust
Language:SystemVerilog00
opentitan
OpenTitan: Open source silicon root of trust
Language:SystemVerilog2.6k 106 6.9k792

gdessouky's Repositories

gdessouky/hackdac_2018_beta
The SoC used for the beta phase of Hack@DAC 2018.
Language:SystemVerilog6 1 00
gdessouky/cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
Language:SystemVerilog0 0 00
gdessouky/opentitan
OpenTitan: Open source silicon root of trust
Language:SystemVerilog00