| File | Description |
|---|---|
| fir.v | Verilog design |
| fir_tb.v | Testbench for fir.v |
| fir_utilization_synth.rpt | Synthesis report |
| runme.log | Synthesis log |
| simulate.log | Behavioral simulation log |
| timing_report.txt | Timing report |
| SoC_Lab3.pdf | Lab report |
Configuraion write (AXI-Lite)
Tap read back (AXI-Lite)
ap_start (ap_config_reg[0]) asserted @965ns
ap_done (ap_config_reg[1]) asserted @78,975ns
#cycle from ap_start to ap_done = (78,975-965)/cycle time(10ns) = 7801 cycles
X[n] stream in(AXI-Stream Slave)
Y[n] stream out(AXI-Stream Master)
