/FPGA-Otsu

Verilog Implementation of Otsu's algorithm

Primary LanguageVerilog

FPGA-Otsu

Verilog Implementation of Otsu's algorithm

To Run

  1. Resize Images to 768x512
  2. Convert image to .bmp format
  3. Extract .hex file using bmp2hex.m using matlab
  4. run tb_simulation in Xilinx ISE
  5. in simulation console, type: run 6ms.