/panologic-g2

Pano Logic G2 Reverse Engineering Project

Primary LanguageVerilogApache License 2.0Apache-2.0

Pano Logic Zero Client G2

Introduction

This project contains the reverse engineering results of the Pano Logic Zero Client G2.

It was started by cyrozap, who did all the hard work of figuring out connections between the FPGA and peripheral ICs. Some of this work can also be found on his wiki page, though this GitHub repo should now all have that information as well.

The Pano Logic G2 is the successor of the Pano Logic G1. Like the G1, it has all the interfaces that are needed to build a small mini-computer with an FPGA.

Compared to the G1, the most important improvements of G2 are:

  • Much larger FPGA: a Xilinx Spartan-6 XC6SLX150 instead of a Xilinx Spartan-3E XC3S1600E.

    This is one of the largest Spartan-6 devices, with 147k logic cells, 1.3Mbit of block RAM and 180 DSPs. A huge upgrade compared to the 33k logic cells, 231kbit of block RAM and 36 multipliers of the G1 FPGA.

    Unfortunately, this FPGA is also the biggest disadvantage: it's not supported by the free Xilinx Webpack version of ISE!

    Since the commercial version costs many thousands of dollars, this makes this device out of reach for more, if not all, hobbyists.

  • 256MByte of DDR2 SDRAM instead of 32MByte of LPDDR SDRAM.

  • 128Mbit serial flash instead of 8Mbit.

  • DVI instead of VGA output

  • Micro-HDMI output

  • Gigabit Ethernet

Disassembly

Overly detailed disassembly pictures can be found here.

Disassembly Complete

JTAG

Instructions on how to get the JTAG going are here.

FPGA Connections

See the Pano.ucf file for all the FPGA connections.

There were all reverse engineered by cyrozap.

Resources