Pano Logic Zero Client G2
Introduction
This project contains the reverse engineering results of the Pano Logic Zero Client G2.
It was started by cyrozap, who did all the hard work of figuring out connections between the FPGA and peripheral ICs. Some of this work can also be found on his wiki page, though this GitHub repo should now all have that information as well.
The Pano Logic G2 is the successor of the Pano Logic G1. Like the G1, it has all the interfaces that are needed to build a small mini-computer with an FPGA.
Compared to the G1, the most important improvements of G2 are:
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Much larger FPGA: a Xilinx Spartan-6 XC6SLX150 instead of a Xilinx Spartan-3E XC3S1600E.
This is one of the largest Spartan-6 devices, with 147k logic cells, 1.3Mbit of block RAM and 180 DSPs. A huge upgrade compared to the 33k logic cells, 231kbit of block RAM and 36 multipliers of the G1 FPGA.
Unfortunately, this FPGA is also the biggest disadvantage: it's not supported by the free Xilinx Webpack version of ISE!
Since the commercial version costs many thousands of dollars, this makes this device out of reach for more, if not all, hobbyists.
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256MByte of DDR2 SDRAM instead of 32MByte of LPDDR SDRAM.
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128Mbit serial flash instead of 8Mbit.
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DVI instead of VGA output
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Micro-HDMI output
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Gigabit Ethernet
Disassembly
Overly detailed disassembly pictures can be found here.
JTAG
Instructions on how to get the JTAG going are here.
FPGA Connections
See the Pano.ucf file for all the FPGA connections.
There were all reverse engineered by cyrozap.
Resources
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Xilinx Spartan-6 XC6SLX150 FGG484 (Speed Grade 2)
Features:
- 147K logic cells
- 23K slices (4 6-input LUTs per slice, 8 FFs per slice)
- 184K FFs
- 1355Kbit max distributed RAM
- 4824Kbit max block RAM (268 RAMs)
- 180 DSPs (1 18x18 multiplier + pre-addr + accumulator)
- 6 CMTs (2 DCMs and 1 PLL per CMT)
- 4 memory controllers (2 used for the DDR2 SDRAM)
Documents:
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2x Micron MT47H32M16NF-25E DDR2 SDRAM
That's right: there are 2 SDRAM chips on this board! Each one has 512Mbit in x16 configuration, good for 128MByte per DRAM and 256MByte total.
Theoretical peak BW is 3.2GByte/s, which is pretty decent.
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Wolfson WM8750BG Audio Codec
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2x Chrontel CH7301C-TF DVI Transmitter
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Marvell 88E1119R-NNW2
https://www.mikrocontroller.net/attachment/139158/88E1111_DS.pdf is the closest. Both 1111 and 1119R have a regular GMII interface, it should be possible to get this working without.
http://static6.arrow.com/aropdfconversion/80d635a18100a0f0c187b633911ff93001715194/ethernetphypsg_v2_ndafr002.pdf shows the differences.
https://github.com/tardfs/frontend/blob/master/ethertest/xapp1042/marvell_88e1111.c supports the same family of GigE PHYs.
https://github.com/Undrizzle/apps/blob/master/DSDT_3.0/phy/ supports 88E1119R directly and highlights the differences with 88E1111.
Joel Williams' [Atlys Resources] https://joelw.id.au/FPGA/DigilentAtlysResources implemented receiving UDP packets with 88E1111 and Spartan 6, ISE project and Xilinx app note XAPP1042 linked from his page. Open sourced.
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Micron M25P128 Serial Flash with SPI
128Mbit or 32MByte. 54MHz.
Marked as 25P28V6G. Which translates to M25P128 with this code translator.
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SMSC 3300-EKZ USB ULPI to USB PHY Transceiver
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TI LM339 Quad Differential Comparators
Marked L339.