Improper sythesis with Yosis

[Electro707]

Hello,
The following code below does not get properly converted over to Yosys.

--------------------------------------------
-- Module Name: pulldown
--------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity pulldown is
    port (
        in_swt : inout std_logic_vector(7 downto 0);
        clk : in std_logic;
        swt_state : out std_logic_vector(7 downto 0)
    );
end pulldown;

architecture behavior of pulldown is

    signal clk_count : unsigned(3 downto 0) := (others => '0');
    signal read_enable, read_enable2 : std_logic := '0';
    signal a : std_logic_vector(7 downto 0);

    begin
        process (clk)
            begin
            if (clk' event and clk = '1') then --CLK rising edge
                clk_count <= clk_count + 1;

                a <= in_swt;

                if (clk_count(2) = '1') then
                    read_enable <= not(read_enable);
                    clk_count <= (others => '0');
                end if;
            end if;

        end process;

        process (read_enable, in_swt)
            begin
            if (read_enable = '1') then
                in_swt <= (others => 'Z');
            else
                swt_state <= a;
                in_swt <= (others => '0');
            end if;
        end process;

end architecture;

If one is to run
yosys -m ghdl -p 'ghdl --std=93 --latches -fsynopsys pulldown; write_verilog pulldown.v''
The output looks like the following, which is not what should happen:

/* Generated by Yosys 0.21 (git sha1 e6d2a900a9, gcc 11.2.0-19ubuntu1 -fPIC -Os) */

module \pulldown (clk, in_swt, swt_state);
  wire [7:0] _0_;
  wire [7:0] _1_;
  wire _2_;
  wire _3_;
  wire [7:0] _4_;
  reg [7:0] _5_ = 8'h00;
  wire _6_;
  reg _7_ = 1'h0;
  reg [7:0] _8_;
  wire [7:0] _9_;
  wire [7:0] a;
  input clk;
  wire clk;
  wire [7:0] clk_count;
  inout [7:0] in_swt;
  wire [7:0] in_swt;
  wire read_enable;
  output [7:0] swt_state;
  wire [7:0] swt_state;
  assign _2_ = $signed({ 1'h0, clk_count }) > $signed(9'h002);
  assign _3_ = ~ read_enable;
  assign _4_ = _2_ ? 8'h00 : _0_;
  always @(posedge clk)
    _5_ <= _4_;
  assign _6_ = _2_ ? _3_ : read_enable;
  always @(posedge clk)
    _7_ <= _6_;
  always @(posedge clk)
    _8_ <= in_swt;
  assign _9_ = read_enable ? 8'hzz : 8'h00;
  assign _1_ = read_enable ? a : _1_;
  assign _0_ = clk_count + 8'h01;
  assign in_swt = _9_;
  assign clk_count = _5_;
  assign read_enable = _7_;
  assign a = _8_;
  assign swt_state = _1_;
endmodule

The program does get synthesized properly in IceCube2. If I simulate it in ghdl the waveform looks about expected (with the output bits either going to 0 or H depending on the input, and in hardware the H would show up as a 1 due to the capacitance of the button's pins)

I do know if I am doing something out of standard or if this is a bug with this repo, but I've spend the past 4 hours trying to figure it out with no avail.

The program's goals is to simulate a pullup resistor due to it missing on a FPGA board (https://forum.alchitry.com/thread-6.html)

NOTE:

This issue is closed because the main issue was with nextpnr-ice40, adding the --force flag brings it up to a similar-ish working state as IceCube2 (the output is oscillating, so might be a problem with yosys or nextpnr). Sorry for the non-issue Issue.
If you do stumble upon this Issue and see something I can improve on in the HDL code, feel free to let me know.
Also, if there is a forum for these questions that is geared towards ghdl/yosys, feel free to point me to the right site.