ghdl/ghdl-yosys-plugin

Issues

• Hierarchical signal names not escaped properly when synthesised to Verilog

  #200 opened 3 months ago by aquohn
  0

• Blackbox

  #199 opened 5 months ago by AdamKeith1
  0

• Report statment and states in vhdl

  #198 opened 6 months ago by aniketabhiraj2004
  1

• Error building ghdl plugin for yosys

  #168 opened 3 years ago by minghunghw
  14

• How to run unisim using cxxrtl

  #197 opened 6 months ago by aniketabhiraj2004
  7

• GHDL+YOSYS formal verification, using Xilinx primitives

  #194 opened 6 months ago by Marceloqa
  3

• Wrongly assign the name internal signal for vhdl

  #196 opened 7 months ago by aniketabhiraj2004
  2

• libgnat-13.so module missing

  #195 opened 7 months ago by 95lux
  2

• Error when using plugin on M1 mac

  #193 opened a year ago by joaocolombari
  1

• wire not found for $posedge

  #192 opened a year ago by GyrosGeier
  3

• Unable to build the plugin

  #175 opened 2 years ago by canerbulduk
  3

• Another case of "wire not found for $posedge" - related to async resets?

  #164 opened 3 years ago by robinsonb5
  3

• Please note that open-tool-forge/fpga-toolchain is no longer maintained

  #172 opened a year ago by jockm
  1

• The project Keccak_PPL has several VHDL compilation issues (Fails to synthesize).

  #190 opened a year ago by alaindargelas
  0

• The pre-built option #1 is extreamly outdated

  #189 opened a year ago by rodrigomelo9
  1

• Upload of ghdl-yosys-plugin to Debian?

  #162 opened 2 years ago by smoe
  7

• 64 bits slicing problem

  #188 opened 2 years ago by Martoni
  2

• Unable to build plugin

  #187 opened 2 years ago by 48004800
  30

• ERROR: wire not found for $posedge

  #146 opened 4 years ago by stevenbell
  3

• ECP5 Example fails: 'VLO' is unsupported

  #184 opened 2 years ago by playduck
  3

• Failure to compile - ERROR: Assert `n.id != 0' failed in src/ghdl.cc:204.

  #183 opened 2 years ago by psi-chuffine
  2

• Error when using altera_mf lib

  #179 opened 2 years ago by albydnc
  4

• ERROR: No such command: ghdl (type 'help' for a command overview)

  #182 opened 2 years ago by wklam296
  5

• Linking against libgnat-9.so.1

  #181 opened 2 years ago by jjjt-git
  10

• Assertion error on synth-vhdl_expr.adb while importing entity into yosys

  #180 opened 2 years ago by KelvinChung2000
  3

• error: clocked logic requires clocked logic on else part

  #177 opened 2 years ago by ibkvictor
  3

• ERROR: wire not found for $posedge

  #178 opened 2 years ago by ibkvictor
  3

• Error when using inout record

  #176 opened 2 years ago by albydnc
  3

• Error with altera vendor libraries

  #174 opened 2 years ago by albydnc
  4

• Improper sythesis with Yosis

  #173 opened 2 years ago by Electro707
  0

• make fails

  #149 opened 4 years ago by 71GA
  26

• Use of BRAM in ICE40 ...

  #165 opened 3 years ago by PPlinux
  2

• High impedance assignment translates to 1'x

  #170 opened 2 years ago by DanielG
  6

• VHDL to Verilog conversion with yosys-ghdl-plugin -- how to perserve signal names

  #153 opened 3 years ago by 71GA
  4

• Roadmap for a release

  #167 opened 3 years ago by Martoni
  1

• wire not found for $posedge

  #163 opened 3 years ago by kammoh
  3

• Build library type mismatch

  #150 opened 3 years ago by jeinstei
  24

• make fails: unknown commands: "--libghdl-library-path" & "--libghdl-include-dir"

  #161 opened 3 years ago by tortik92
  40

• ERROR: Assert `n.id != 0' failed - seems related to unassigned variables

  #159 opened 3 years ago by JulianKemmerer
  7

• Yosys assert: is_fully_const() && GetSize(chunks_) <= 1 failed in kernel/rtlil.cc:4532

  #160 opened 3 years ago by antonblanchard
  2

• Unable to synthesize large design

  #144 opened 3 years ago by monideepbora
  2

• GHDL VHDL support

  #147 opened 3 years ago by PPlinux
  7

• raised STORAGE_ERROR : stack overflow or erroneous memory access

  #158 opened 3 years ago by suarezvictor
  13

• Support for 'keep' boolean attribute

  #154 opened 3 years ago by anfractuosity
  1

• Case sensitivity issue

  #155 opened 3 years ago by SiliconWizard
  8

• Error: Info: No candidate top level module

  #157 opened 3 years ago by sowana
  3

• Add support for Yosys $live cell (needed for liveness proofs)

  #152 opened 3 years ago by tmeissner
  2

• ID::blackbox is not defined

  #151 opened 3 years ago by Rachus
  1

• GHDL synthesis - beginner question

  #148 opened 4 years ago by etnapoli
  3

• RD_TRANSPARENT not set correctly for memories

  #145 opened 4 years ago by MJoergen
  3