giovannipollo/DLX-RISC-CPU

DLX RISC Processor implementation with extended instruction set and windowed register file

DLX - A RISC CPU

The DLX is a RISC processor architecture designed by John L. Hennessy and David A. Patterson, the principal designers of the Stanford MIPS and the Berkeley RISC designs (respectively), the two benchmark examples of RISC design (named after the Berkeley design).

We adopted this architecture by implemented our own design, with additional features: - Extended Intruction Set - Windowed Register File with enhanced subroutines call and return