The Constructing Hardware in a Scala Embedded Language (Chisel) is an open-source hardware description language (HDL) used to describe digital electronics and circuits at the register-transfer level that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs.
Chisel adds hardware construction primitives to the Scala programming language, providing designers with the power of a modern programming language to write complex, parameterizable circuit generators that produce synthesizable Verilog. This generator methodology enables the creation of re-usable components and libraries, such as the FIFO queue and arbiters in the Chisel Standard Library, raising the level of abstraction in design while retaining fine-grained control.
For more information on the benefits of Chisel see: "What benefits does Chisel offer over classic Hardware Description Languages?"
Chisel is powered by FIRRTL (Flexible Intermediate Representation for RTL), a hardware compiler framework that performs optimizations of Chisel-generated circuits and supports custom user-defined circuit transformations.
import chisel3._
import chisel3.util._
class Blinky(freq: Int, startOn: Boolean = false) extends Module {
val io = IO(new Bundle {
val led0 = Output(Bool())
})
// Blink LED every second using Chisel built-in util.Counter
val led = RegInit(startOn.B)
val (_, counterWrap) = Counter(true.B, freq / 2)
when(counterWrap) {
led := ~led
}
io.led0 := led
}
object Main extends App {
// These lines generate the Verilog output
println(
new (chisel3.stage.ChiselStage).emitVerilog(
new Blinky(1000),
Array(
"--emission-options=disableMemRandomization,disableRegisterRandomization"
)
)
)
}Should output the following Verilog:
Click to expand!
module Blinky(
input clock,
input reset,
output io_led0
);
reg led; // @[main.scala 11:20]
reg [8:0] counterWrap_value; // @[Counter.scala 62:40]
wire counterWrap_wrap_wrap = counterWrap_value == 9'h1f3; // @[Counter.scala 74:24]
wire [8:0] _counterWrap_wrap_value_T_1 = counterWrap_value + 9'h1; // @[Counter.scala 78:24]
assign io_led0 = led; // @[main.scala 16:11]
always @(posedge clock) begin
if (reset) begin // @[main.scala 11:20]
led <= 1'h0; // @[main.scala 11:20]
end else if (counterWrap_wrap_wrap) begin // @[main.scala 13:21]
led <= ~led; // @[main.scala 14:9]
end
if (reset) begin // @[Counter.scala 62:40]
counterWrap_value <= 9'h0; // @[Counter.scala 62:40]
end else if (counterWrap_wrap_wrap) begin // @[Counter.scala 88:20]
counterWrap_value <= 9'h0; // @[Counter.scala 88:28]
end else begin
counterWrap_value <= _counterWrap_wrap_value_T_1; // @[Counter.scala 78:15]
end
end
endmodule
Consider an FIR filter that implements a convolution operation, as depicted in this block diagram:
While Chisel provides similar base primitives as synthesizable Verilog, and could be used as such:
// 3-point moving sum implemented in the style of a FIR filter
class MovingSum3(bitWidth: Int) extends Module {
val io = IO(new Bundle {
val in = Input(UInt(bitWidth.W))
val out = Output(UInt(bitWidth.W))
})
val z1 = RegNext(io.in)
val z2 = RegNext(z1)
io.out := (io.in * 1.U) + (z1 * 1.U) + (z2 * 1.U)
}the power of Chisel comes from the ability to create generators, such as an FIR filter that is defined by the list of coefficients:
// Generalized FIR filter parameterized by the convolution coefficients
class FirFilter(bitWidth: Int, coeffs: Seq[UInt]) extends Module {
val io = IO(new Bundle {
val in = Input(UInt(bitWidth.W))
val out = Output(UInt(bitWidth.W))
})
// Create the serial-in, parallel-out shift register
val zs = Reg(Vec(coeffs.length, UInt(bitWidth.W)))
zs(0) := io.in
for (i <- 1 until coeffs.length) {
zs(i) := zs(i-1)
}
// Do the multiplies
val products = VecInit.tabulate(coeffs.length)(i => zs(i) * coeffs(i))
// Sum up the products
io.out := products.reduce(_ + _)
}and use and re-use them across designs:
val movingSum3Filter = Module(new FirFilter(8, Seq(1.U, 1.U, 1.U))) // same 3-point moving sum filter as before
val delayFilter = Module(new FirFilter(8, Seq(0.U, 1.U))) // 1-cycle delay as a FIR filter
val triangleFilter = Module(new FirFilter(8, Seq(1.U, 2.U, 3.U, 2.U, 1.U))) // 5-point FIR filter with a triangle impulse responseThe above can be converted to Verilog using ChiselStage:
import chisel3.stage.{ChiselStage, ChiselGeneratorAnnotation}
(new chisel3.stage.ChiselStage).execute(
Array("-X", "verilog"),
Seq(ChiselGeneratorAnnotation(() => new FirFilter(8, Seq(1.U, 1.U, 1.U)))))Alternatively, you may generate some Verilog directly for inspection:
val verilogString = chisel3.emitVerilog(new FirFilter(8, Seq(0.U, 1.U)))
println(verilogString)The online Chisel Bootcamp is the recommended way to get started with and learn Chisel. No setup is required (it runs in the browser), nor does it assume any prior knowledge of Scala.
The classic Chisel tutorial contains small exercises and runs on your computer.
If you like a textbook to learn Chisel and also a bit of digital design in general, you may be interested in reading Digital Design with Chisel. It is available in English, Chinese, Japanese, and Vietnamese.
See the setup instructions for how to set up your environment to build Chisel locally.
When you're ready to build your own circuits in Chisel, we recommend starting from the Chisel Template repository, which provides a pre-configured project, example design, and testbench. Follow the chisel-template README to get started.
If you insist on setting up your own project from scratch, your project needs to depend on both the chisel3-plugin (Scalac plugin) and the chisel3 library. For example, in SBT this could be expressed as:
// build.sbt
scalaVersion := "2.13.8"
addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "3.5.3" cross CrossVersion.full)
libraryDependencies += "edu.berkeley.cs" %% "chisel3" % "3.5.3"
// We also recommend using chiseltest for writing unit tests
libraryDependencies += "edu.berkeley.cs" %% "chiseltest" % "0.5.3" % "test"If you are trying to make a contribution to this project, please read CONTRIBUTING.md
These simulation-based verification tools are available for Chisel:
- chiseltest is the batteries-included testing and formal verification library for Chisel-based RTL designs and a replacement for the former PeekPokeTester, providing the same base constructs but with a streamlined interface and concurrency support with
forkandjoinwith internal and Verilator integration for simulations.
- Cheat Sheet, a 2-page reference of the base Chisel syntax and libraries
- ScalaDoc, a listing, description, and examples of the functionality exposed by Chisel
- Gitter, where you can ask questions or discuss anything Chisel
- Website (source)
- Scastie (3.5.3)
- asic-world If you aren't familiar with verilog, this is a good tutorial.
If you are migrating from Chisel2, see the migration guide.
Chisel/FIRRTL development meetings happen every Monday and Tuesday from 1100--1200 PT.
Call-in info and meeting notes are available here.
These are the base data types for defining circuit components:
This section describes how to get started contributing to Chisel itself, including how to test your version locally against other projects that pull in Chisel using sbt's managed dependencies.
The Useful Resources for users are also helpful for contributors.
- Chisel Breakdown Slides, an introductory talk about Chisel's internals
You must first install required dependencies to build Chisel locally, please see the setup instructions.
Clone and build the Chisel library:
git clone https://github.com/chipsalliance/chisel3.git
cd chisel3
sbt compileIn order to run the following unit tests, you will need several tools on your PATH, namely
verilator,
yosys,
espresso,
and z3.
Check that each is installed on your PATH by running which verilator and so on.
If the compilation succeeded and the dependencies noted above are installed, you can then run the included unit tests by invoking:
sbt testTo use the development version of Chisel (master branch), you will need to build from source and publishLocal.
The repository version can be found in the build.sbt file.
As of the time of writing it was:
version := "3.6-SNAPSHOT"To publish your version of Chisel to the local Ivy (sbt's dependency manager) repository, run:
sbt publishLocalThe compiled version gets placed in ~/.ivy2/local/edu.berkeley.cs/.
If you need to un-publish your local copy of Chisel, remove the directory generated in ~/.ivy2/local/edu.berkeley.cs/.
In order to have your projects use this version of Chisel, you should update the libraryDependencies setting in your project's build.sbt file to:
libraryDependencies += "edu.berkeley.cs" %% "chisel3" % "3.6-SNAPSHOT"While we recommend using the library dependency approach as described above, it is possible to build Chisel and FIRRTL in a single SBT project.
Caveats:
- This only works for the "main" configuration; you cannot build the Chisel tests this way because
treadleis only supported as a library dependency. - Do not
publishLocalwhen building this way. The published artifact will be missing the FIRRTL dependency.
This works by using sbt-sriracha, an SBT plugin for toggling between source and library dependencies. It provides two JVM system properties that, when set, will tell SBT to include FIRRTL as a source project:
sbt.sourcemode- when set to true, SBT will look for FIRRTL in the workspacesbt.workspace- sets the root directory of the workspace
Example use:
# From root of this repo
git clone git@github.com:chipsalliance/firrtl.git
sbt -Dsbt.sourcemode=true -Dsbt.workspace=$PWDThis is primarily useful for building projects that themselves want to include Chisel as a source dependency. As an example, see Rocket Chip
The Chisel3 compiler consists of these main parts:
- The frontend,
chisel3.*, which is the publicly visible "API" of Chisel and what is used in Chisel RTL. These just add data to the... - The Builder,
chisel3.internal.Builder, which maintains global state (like the currently open Module) and contains commands, generating... - The intermediate data structures,
chisel3.firrtl.*, which are syntactically very similar to Firrtl. Once the entire circuit has been elaborated, the top-level object (aCircuit) is then passed to... - The Firrtl emitter,
chisel3.firrtl.Emitter, which turns the intermediate data structures into a string that can be written out into a Firrtl file for further processing.
Also included is:
- The standard library of circuit generators,
chisel3.util.*. These contain commonly used interfaces and constructors (likeDecoupled, which wraps a signal with a ready-valid pair) as well as fully parameterizable circuit generators (like arbiters and multiplexors). - Chisel Stage,
chisel3.stage.*, which contains compilation and test functions that are invoked in the standard Verilog generation and simulation testing infrastructure. These can also be used as part of custom flows.
Chisel consists of 4 Scala projects; each is its own separate compilation unit:
coreis the bulk of the source code of Chisel, depends onmacrossrc/mainis the "main" that brings it all together and includes autillibrary, which depends oncorepluginis the compiler plugin, no internal dependenciesmacrosis most of the macros used in Chisel, no internal dependencies
Code that touches lots of APIs that are private to the chisel3 package should belong in core, while code that is pure Chisel should belong in src/main.
We encourage Chisel users (as opposed to Chisel developers), to use the latest release version of Chisel. This chisel-template repository is kept up-to-date, depending on the most recent version of Chisel. The recommended version is also captured near the top of this README, and in the Github releases section of this repo. If you encounter an issue with a released version of Chisel, please file an issue on GitHub mentioning the Chisel version and provide a simple test case (if possible). Try to reproduce the issue with the associated latest minor release (to verify that the issue hasn't been addressed).
For more information on our versioning policy and what versions of the various Chisel ecosystem projects work together, see Chisel Project Versioning.
If you're developing a Chisel library (or chisel3 itself), you'll probably want to work closer to the tip of the development trunk.
By default, the master branches of the chisel repositories are configured to build and publish their version of the code as Z.Y-SNAPSHOT.
Updated SNAPSHOTs are publised on every push to master.
You are encouraged to do your development against the latest SNAPSHOT, but note that neither API nor ABI compatibility is guaranteed so your code may break at any time.