This package provides useful extensions on top of vhdl-mode
and vhdl-ts-mode
.
- Tree-sitter
vhdl-ts-mode
support - Project management
- Improve syntax highlighting
- Find definitions and references
- Auto-completion
- Hierarchy extraction and navigation
- LSP configuration for
lsp-bridge
,lsp-mode
,eglot
andlspce
- Support for many linters via
flycheck
- Beautify blocks and instances
- Navigate through instances in a entity
- Templates insertion via
hydra
- Compilation with colored errors/warnings and jump to file/line
- Improve
imenu
, detect instances - Enhanced support for
which-func
- Improve code folding via
hideshow
- Auto-configure
time-stamp
- Port connection utilities
- Emacs 29.1+
- Feature-specific binaries
Tree-sitter is optional but recommended and only required if using vhdl-ts-mode
for some of the features above.
For more info, see the wiki.
vhdl-ext
is available on MELPA.
To install it via straight with use-package
:
(straight-use-package 'use-package)
(use-package vhdl-ext)
The most basic configuration just requires choosing which features you
want to load, setup the minor-mode and add it as a hook for vhdl-mode
.
By default all features are enabled:
;; Can also be set through `M-x RET customize-group RET vhdl-ext':
;; Comment out/remove the ones you do not need
(setq vhdl-ext-feature-list
'(font-lock
xref
capf
hierarchy
eglot
lsp
lsp-bridge
lspce
flycheck
beautify
navigation
template
compilation
imenu
which-func
hideshow
time-stamp
ports))
(require 'vhdl-ext)
(vhdl-ext-mode-setup)
(add-hook 'vhdl-mode-hook #'vhdl-ext-mode)
If installed and loaded via use-package
:
(use-package vhdl-ext
:hook ((vhdl-mode . vhdl-ext-mode))
:init
;; Can also be set through `M-x RET customize-group RET vhdl-ext':
;; Comment out/remove the ones you do not need
(setq vhdl-ext-feature-list
'(font-lock
xref
capf
hierarchy
eglot
lsp
lsp-bridge
lspce
flycheck
beautify
navigation
template
compilation
imenu
which-func
hideshow
time-stamp
ports))
:config
(vhdl-ext-mode-setup))
Enabling of vhdl-ext-mode
minor-mode creates the following keybindings:
-
Features
- C-M-i
vhdl-ext-beautify-block-at-point
- C-c C-v
vhdl-ext-hierarchy-current-buffer
- C-c C-t
vhdl-ext-hydra/body
- C-c C-f
vhdl-ext-flycheck-mode
- C-c C-u>
vhdl-ext-tags-get
- C-c <f5>
vhdl-ext-compile-project-ghdl
- C-M-i
-
Navigation
- C-M-f
vhdl-ext-forward-sexp
- C-M-b
vhdl-ext-backward-sexp
- C-M-u
vhdl-ext-find-entity-instance-bwd
- C-M-d
vhdl-ext-find-entity-instance-fwd
- C-M-.
vhdl-ext-jump-to-parent-entity
- C-c M-.
vhdl-ext-jump-to-entity-at-point-def
- C-c M-?
vhdl-ext-jump-to-entity-at-point-ref
- C-M-f
-
Port connections
- C-c C-c t
vhdl-ext-ports-toggle-connect
- C-c C-c r
vhdl-ext-ports-connect-recursively
- C-c C-c t
Some of the features that vhdl-ext
provides are based either on
builtin vhdl-mode
Emacs lisp parsing or on tree-sitter
vhdl-ts-mode
:
- Hierarchy extraction can use both builtin Elisp parsing and tree-sitter
- Using tree-sitter as a backend is recommended as it is much faster, efficient and accurate
- Tags collection for completion and navigation of definitions and references requires tree-sitter
For information about installation of vhdl-ts-mode
check its
repo.
The package provides the variable vhdl-ext-project-alist
to
select which files belong to a specific project:
(setq vhdl-ext-project-alist
`(("axi_if_converter" ; Project name
:root "/home/gonz/Repos/larumbe/axi_if_converter" ; supports remote dirs via Tramp
:files ("src/my_block.vhd"
"src/*.vhd") ; Multiple files can be specified through the glob pattern
:dirs ("src/tb"
"-r src/rtl" ; -r to add directories recursively
"src/syn/*_block"
"src/**/netlists") ; add all dirs that begin with "src" and end with "netlists"
:ignore-dirs ("src/ignored_ip")
:ignore-files ("src/some_ip/ignored_sim_netlist.vhd")
;; The ones below are used for GHDL-related features
:worklib "xil_defaultlib" ; Defaults to `work' if not set
:workdir "library/xil_defaultlib" ; Output compilation directory for worklib
:lib-search-path ("/opt/ghdl_Xilinx_lib/")))) ; Extra directories to look for compiled libraries
The different properties for each project entry determine which files will be used for some features of the package, such as completion, xref navigation, hierarchy extraction and compilation.
For configuration information, see the wiki.
vhdl-ext
provides a builtin xref
backend to navigate definitions and references of current project in vhdl-ext-project-alist
.
![](https://private-user-images.githubusercontent.com/51021955/268115773-7fde4bc6-0c84-4da0-8e37-6a0e0dac36f6.gif?jwt=eyJhbGciOiJIUzI1NiIsInR5cCI6IkpXVCJ9.eyJpc3MiOiJnaXRodWIuY29tIiwiYXVkIjoicmF3LmdpdGh1YnVzZXJjb250ZW50LmNvbSIsImtleSI6ImtleTUiLCJleHAiOjE3MjI5NDMxMTksIm5iZiI6MTcyMjk0MjgxOSwicGF0aCI6Ii81MTAyMTk1NS8yNjgxMTU3NzMtN2ZkZTRiYzYtMGM4NC00ZGEwLThlMzctNmEwZTBkYWMzNmY2LmdpZj9YLUFtei1BbGdvcml0aG09QVdTNC1ITUFDLVNIQTI1NiZYLUFtei1DcmVkZW50aWFsPUFLSUFWQ09EWUxTQTUzUFFLNFpBJTJGMjAyNDA4MDYlMkZ1cy1lYXN0LTElMkZzMyUyRmF3czRfcmVxdWVzdCZYLUFtei1EYXRlPTIwMjQwODA2VDExMTMzOVomWC1BbXotRXhwaXJlcz0zMDAmWC1BbXotU2lnbmF0dXJlPWM5M2E4NzI1NzI2YWUzOTYzNWY4ZTcwZTQyN2Q1NzQ4YjRiOTEzMjVkODAwMGMzYmRmMGM1MTkyOTgzZTY5ZGYmWC1BbXotU2lnbmVkSGVhZGVycz1ob3N0JmFjdG9yX2lkPTAma2V5X2lkPTAmcmVwb19pZD0wIn0.-_A2VIFmXxGkDwTyCzGorDZyd9Umg__j8zJGE9OK6II)
For configuration information, see the wiki.
Complete with tags from current VHDL project.
![](https://private-user-images.githubusercontent.com/51021955/268114091-4c908a17-df9e-4fb3-8263-e5e302700ac9.gif?jwt=eyJhbGciOiJIUzI1NiIsInR5cCI6IkpXVCJ9.eyJpc3MiOiJnaXRodWIuY29tIiwiYXVkIjoicmF3LmdpdGh1YnVzZXJjb250ZW50LmNvbSIsImtleSI6ImtleTUiLCJleHAiOjE3MjI5NDMxMTksIm5iZiI6MTcyMjk0MjgxOSwicGF0aCI6Ii81MTAyMTk1NS8yNjgxMTQwOTEtNGM5MDhhMTctZGY5ZS00ZmIzLTgyNjMtZTVlMzAyNzAwYWM5LmdpZj9YLUFtei1BbGdvcml0aG09QVdTNC1ITUFDLVNIQTI1NiZYLUFtei1DcmVkZW50aWFsPUFLSUFWQ09EWUxTQTUzUFFLNFpBJTJGMjAyNDA4MDYlMkZ1cy1lYXN0LTElMkZzMyUyRmF3czRfcmVxdWVzdCZYLUFtei1EYXRlPTIwMjQwODA2VDExMTMzOVomWC1BbXotRXhwaXJlcz0zMDAmWC1BbXotU2lnbmF0dXJlPTQ0MzBiMjZiYzAwYWQxYjQ1N2VkYmZkY2NhZWEwY2EwZWU0Njg3NjZhNmFlNjk5ZGJjZTgwZWJjZjU1NmUyNjMmWC1BbXotU2lnbmVkSGVhZGVycz1ob3N0JmFjdG9yX2lkPTAma2V5X2lkPTAmcmVwb19pZD0wIn0.FdkjrMShWV6kQV_KU-UHezeHEBbKpDEV0jgxYO6whNg)
For configuration information, see the wiki.
Hierarchy extraction of entity at current buffer.
![](https://private-user-images.githubusercontent.com/51021955/259072407-79018dc4-833a-4ce6-9f2b-3195ba75481d.gif?jwt=eyJhbGciOiJIUzI1NiIsInR5cCI6IkpXVCJ9.eyJpc3MiOiJnaXRodWIuY29tIiwiYXVkIjoicmF3LmdpdGh1YnVzZXJjb250ZW50LmNvbSIsImtleSI6ImtleTUiLCJleHAiOjE3MjI5NDMxMTksIm5iZiI6MTcyMjk0MjgxOSwicGF0aCI6Ii81MTAyMTk1NS8yNTkwNzI0MDctNzkwMThkYzQtODMzYS00Y2U2LTlmMmItMzE5NWJhNzU0ODFkLmdpZj9YLUFtei1BbGdvcml0aG09QVdTNC1ITUFDLVNIQTI1NiZYLUFtei1DcmVkZW50aWFsPUFLSUFWQ09EWUxTQTUzUFFLNFpBJTJGMjAyNDA4MDYlMkZ1cy1lYXN0LTElMkZzMyUyRmF3czRfcmVxdWVzdCZYLUFtei1EYXRlPTIwMjQwODA2VDExMTMzOVomWC1BbXotRXhwaXJlcz0zMDAmWC1BbXotU2lnbmF0dXJlPWQwNTYxM2NhMGQyYzVkZTJjNWJhYjMxOWZiOTBiOGJkZDk5OGQwYTYzMDI3MDI5YmZkOWVmZTUzOTk5ZmUzNzkmWC1BbXotU2lnbmVkSGVhZGVycz1ob3N0JmFjdG9yX2lkPTAma2V5X2lkPTAmcmVwb19pZD0wIn0.D4VlPyQLhCHbJTx6LnbKElidx-gkWpBI61Wkmb2-2jM)
For configuration information, see the wiki.
Auto-configure various VHDL language servers for lsp-bridge
, lsp-mode
, eglot
and lspce
:
For configuration instructions, see the wiki.
Support via flycheck
for the following linters:
For configuration and usage instructions, see the wiki
Beautify block and instances at point:
![](https://private-user-images.githubusercontent.com/51021955/259073901-cffb0c9d-3a39-4e58-b422-fb275db124a8.gif?jwt=eyJhbGciOiJIUzI1NiIsInR5cCI6IkpXVCJ9.eyJpc3MiOiJnaXRodWIuY29tIiwiYXVkIjoicmF3LmdpdGh1YnVzZXJjb250ZW50LmNvbSIsImtleSI6ImtleTUiLCJleHAiOjE3MjI5NDMxMTksIm5iZiI6MTcyMjk0MjgxOSwicGF0aCI6Ii81MTAyMTk1NS8yNTkwNzM5MDEtY2ZmYjBjOWQtM2EzOS00ZTU4LWI0MjItZmIyNzVkYjEyNGE4LmdpZj9YLUFtei1BbGdvcml0aG09QVdTNC1ITUFDLVNIQTI1NiZYLUFtei1DcmVkZW50aWFsPUFLSUFWQ09EWUxTQTUzUFFLNFpBJTJGMjAyNDA4MDYlMkZ1cy1lYXN0LTElMkZzMyUyRmF3czRfcmVxdWVzdCZYLUFtei1EYXRlPTIwMjQwODA2VDExMTMzOVomWC1BbXotRXhwaXJlcz0zMDAmWC1BbXotU2lnbmF0dXJlPWU4M2Q0NDkwMTg1MzZmOWE3MzkxNWU1M2U1YzU0NzFlZmJkYjE2OTA3MGY5YTVlMDZkMDAzZWU2MGMwNGEyMTQmWC1BbXotU2lnbmVkSGVhZGVycz1ob3N0JmFjdG9yX2lkPTAma2V5X2lkPTAmcmVwb19pZD0wIn0.LuEqdxMN0V6-Ra9qYH4qMmBFQcyxHtRaa9w2MSN8Low)
Interactive functions:
vhdl-ext-beautify-block-at-point
: C-M-ivhdl-ext-beautify-instance-at-point
Batch-mode functions:
vhdl-ext-beautify-files
vhdl-ext-beautify-dir-files
: uses tree-sitter if run with prefix arg C-u
- Navigate instances inside an entity
- Jump to definition/references of entity at point
- Jump to parent entity
For detailed info see the wiki.
Snippet selection via hydra
.
vhdl-ext-hydra/body
: C-c C-t
Provides functions to perform compilations with syntax highlighting and jump to error:
![](https://private-user-images.githubusercontent.com/51021955/244758196-845980ab-c54b-4e89-b53f-056140be87a7.gif?jwt=eyJhbGciOiJIUzI1NiIsInR5cCI6IkpXVCJ9.eyJpc3MiOiJnaXRodWIuY29tIiwiYXVkIjoicmF3LmdpdGh1YnVzZXJjb250ZW50LmNvbSIsImtleSI6ImtleTUiLCJleHAiOjE3MjI5NDMxMTksIm5iZiI6MTcyMjk0MjgxOSwicGF0aCI6Ii81MTAyMTk1NS8yNDQ3NTgxOTYtODQ1OTgwYWItYzU0Yi00ZTg5LWI1M2YtMDU2MTQwYmU4N2E3LmdpZj9YLUFtei1BbGdvcml0aG09QVdTNC1ITUFDLVNIQTI1NiZYLUFtei1DcmVkZW50aWFsPUFLSUFWQ09EWUxTQTUzUFFLNFpBJTJGMjAyNDA4MDYlMkZ1cy1lYXN0LTElMkZzMyUyRmF3czRfcmVxdWVzdCZYLUFtei1EYXRlPTIwMjQwODA2VDExMTMzOVomWC1BbXotRXhwaXJlcz0zMDAmWC1BbXotU2lnbmF0dXJlPTVkODM1M2VlZGRiYjEwYmE5YTlmYmVlYTcyOTAxZTE0ZTFlNmE2M2M5MDUzNzU1MWZjYjg5OGM5YTc5ZmZkNzkmWC1BbXotU2lnbmVkSGVhZGVycz1ob3N0JmFjdG9yX2lkPTAma2V5X2lkPTAmcmVwb19pZD0wIn0.6t5g2Ug27gMhC5lb_wwa-Y5RKrvWKYFIRqTdLjG762Q)
vhdl-ext-compile-project-ghdl
: C-c <f5>
See more info in the wiki.
Support detection of instances.
Enhanced which-func
support: show current block/instance at point in the mode-line
Improve code folding via hideshow
: add support for if/else/elsif blocks.
Automatic update of header timestamp after file saving.
vhdl-ext-time-stamp-mode
For configuration see wiki
Toggle connections of ports under instance at point:
![](https://private-user-images.githubusercontent.com/51021955/259075601-14536463-a6c4-410f-a890-081f7deb668e.gif?jwt=eyJhbGciOiJIUzI1NiIsInR5cCI6IkpXVCJ9.eyJpc3MiOiJnaXRodWIuY29tIiwiYXVkIjoicmF3LmdpdGh1YnVzZXJjb250ZW50LmNvbSIsImtleSI6ImtleTUiLCJleHAiOjE3MjI5NDMxMTksIm5iZiI6MTcyMjk0MjgxOSwicGF0aCI6Ii81MTAyMTk1NS8yNTkwNzU2MDEtMTQ1MzY0NjMtYTZjNC00MTBmLWE4OTAtMDgxZjdkZWI2NjhlLmdpZj9YLUFtei1BbGdvcml0aG09QVdTNC1ITUFDLVNIQTI1NiZYLUFtei1DcmVkZW50aWFsPUFLSUFWQ09EWUxTQTUzUFFLNFpBJTJGMjAyNDA4MDYlMkZ1cy1lYXN0LTElMkZzMyUyRmF3czRfcmVxdWVzdCZYLUFtei1EYXRlPTIwMjQwODA2VDExMTMzOVomWC1BbXotRXhwaXJlcz0zMDAmWC1BbXotU2lnbmF0dXJlPWZmODRiNDRlZTg3YTdkOTA5N2U4YWJkZGQ1OTdjZDMwZmE5Mzc2Yjk0OWM5MWFlMzNkMWRhNTU0MjVlNjdlZTEmWC1BbXotU2lnbmVkSGVhZGVycz1ob3N0JmFjdG9yX2lkPTAma2V5X2lkPTAmcmVwb19pZD0wIn0.NGd5EZ47XBJ156ZrcR1Qc-_TnDKZ2UbPiyosE81NCSE)
vhdl-ext-ports-toggle-connect
: C-c C-c tvhdl-ext-ports-connect-recursively
: C-c C-c r
Contributions are welcome! Just stick to common Elisp conventions and run the ERT suite after testing your changes and before submitting a new PR.
For new functionality add new ERT tests if possible.
Consider sponsoring to help maintaining the project and for the development of new features. Thank you!
To run the whole ERT test suite change directory to the vhdl-ext
root and make sure test-hdl
Git submodule has been loaded:
git submodule update --init
Then run the default target:
$ make
To run a subset of tests (e.g. navigation):
$ make TESTS=navigation
To regenerate all the expected outputs for the tests:
$ make gen
To regenerate the expected outputs for a group of tests (e.g. navigation):
$ make gen TESTS=navigation
- verilog-ts-mode: SystemVerilog Tree-sitter mode
- vhdl-ts-mode: VHDL Tree-sitter mode
- verilog-ext: SystemVerilog Extensions
- fpga: FPGA & ASIC Utilities for tools of major vendors and open source
- wavedrom-mode: edit and render WaveJSON files to create timing diagrams
- vunit-mode: Integration of VUnit workflow