This is a repo which contains projects of the course Digital Logic Design of Computer Components (SE345) in SJTU in year 2017-2018.
my_first_fpga: A demo project provided by Altera to help you get familiar with FPGA/verilog designing process.stopwatch: A stopwatch. For more details see experiment report.sc_computer: A single-cycle CPU. A truth table is provided and fulfilled. For more details see experiment report.pipe_computer: A pipelined CPU. For more details see experiment report.exp_exam: Solution to the experiment exam. For more details see here.number_game: A number game based on the FPGA board. This is a freely-chosen extension project. For more details see experiment report.- An experiment manual provided by our instructor.
- Usage of the project
my_first_fpga, and Altera-generated files in other projects, should follow Altera's license. - Projects
sc_computer,pipe_computer,exp_examand the experiment manual contain materials provided by instructors/textbook authors/TAs/former students. They should only be used for educational purposes. - Other code completed by myself follows the MIT License.