Bluespec Examples (Bluespexamples)
Design wise examples:
Design |
Description |
half adder |
|
simple multiplier |
|
Communication Protocols |
UART |
Topic wise examples:
Design |
Description |
FIFO |
|
Get Put |
|
Client Server |
|
Connectable |
|
Vectors |
├── Makefile (Make html docs and view)
├── NOTES.adoc (BSV notes)
├── README.adoc (This doc)
├── build (Build folder for all bsv projects)
│ ├── Makefile (Make verilog files and simulate)
│ ├── makefile.inc (Insert file names and path)
│ └── verilog_dir/ (Verilog files compiled from src)
├── src/
│ ├── Common/ (Common files)
| ├── <Designs> (Refer Index)
│ └── workspace/ (Scratch worspace)
└── waveforms/ (Contains all the simulation waveform screenshots)