Pinned Repositories
c-yasg
dummy-add-a-joke-every-time-that-server-is-down
fpga-arty35t-riscv-syntacore-scr1
FPGA-based SDK projects for SCRx cores
msc-sohard-pvs
others-lista-de-empresas
Lista de empresas ou instituições brasileiras que desenvolvem sistemas embarcados
phd-related-works-MEMulator
Memory Emulation on FPGA Boards
phd-related-works-PiMulator
Processing in Memory Emulation
phd-tools-litex
Build your hardware, easily!
riscv-chipsalliance-veer-eh1
VeeR EH1 core
riscv-nox
RISC-V Nox core
gvillanovanm's Repositories
gvillanovanm/c-yasg
gvillanovanm/dummy-add-a-joke-every-time-that-server-is-down
gvillanovanm/fpga-arty35t-riscv-syntacore-scr1
FPGA-based SDK projects for SCRx cores
gvillanovanm/msc-sohard-pvs
gvillanovanm/others-lista-de-empresas
Lista de empresas ou instituições brasileiras que desenvolvem sistemas embarcados
gvillanovanm/phd-related-works-MEMulator
Memory Emulation on FPGA Boards
gvillanovanm/phd-related-works-PiMulator
Processing in Memory Emulation
gvillanovanm/phd-tools-litex
Build your hardware, easily!
gvillanovanm/riscv-chipsalliance-veer-eh1
VeeR EH1 core
gvillanovanm/riscv-nox
RISC-V Nox core
gvillanovanm/riscv-syntacore-scr1
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
gvillanovanm/svlog-adder-amba
gvillanovanm/svlog-aes
gvillanovanm/svlog-axi-uvm
yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/
gvillanovanm/svlog-examples
gvillanovanm/svlog-riscv-dv-uvm
Random instruction generator for RISC-V processor verification
gvillanovanm/svlog-uvm-vscale
a sample UVM testbench, in System Verilog, exercising a RISC-V arithmetic unit
gvillanovanm/verilator-examples
gvillanovanm/vhd-phelma-arm7