gyb1325

32bit-MAC-Unit

32 bit Vedic Multiplier, using the Urdhava Triyagbhayam Sutra Criss Cross method, coded in Verilog

accelergy

Accelergy is an energy estimation infrastructure for accelerator energy estimations

caffe----Ristretto

Ristretto: Caffe-based approximation of convolutional neural networks.

Desent_modification

GPGPU-Ramulator-Simulator

Replace original DRAM model in GPGPU-sim with Ramulator DRAM model

gyb1325.github.io

Github Pages template for academic personal websites, forked from mmistakes/minimal-mistakes

leetcode

My past code on leetcode

Paper_deep_learning

IP for Deep Learning Accelerator

Quantized_1D_layers_keras

Raft-Leader-Election

The assignment to implement a simple leader election of the raft

gyb1325/PipeCNN

An OpenCL-based FPGA Accelerator for Convolutional Neural Networks

gyb1325/FPGA-CNN

This repo is for ECE44x (Fall2015-Spring2016)

gyb1325/GPGPU-Ramulator-Simulator

Replace original DRAM model in GPGPU-sim with Ramulator DRAM model

gyb1325/GPGPUSim-Ramulator

The source code for GPGPUSim+Ramulator simulator. In this version, GPGPUSim uses Ramulator to simulate the DRAM.

gyb1325/RFNoC-HLS-NeuralNet

gyb1325/metaqnn

gyb1325/zynqnet

Master Thesis "ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network"

gyb1325/gpgpu_ramulator

The project that merge gpgpu-sim with ramulator

gyb1325/machine_learning_assignment

gyb1325/benchmarks

gyb1325/algs4

Princeton Algorithm Assignment

gyb1325/Desent_modification

gyb1325/cs_290

The class assignment git

gyb1325/verilog-32-bit-fp-mul

Verilog implementation of a 32-bit floating point multiplier, and a SystemVerilog/Python testbench.

gyb1325/FPGA_Based_CNN

FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.

gyb1325/cudahook

Intercepting CUDA runtime calls with LD_PRELOAD

gyb1325/vhdl-examples

VHDL example code