gzyIDE
I'm an LSI and computer architecture lover, working as an engineer at an image processor fabless vendor.
Pinned Repositories
cbp-tage
TAGE implemented in cbp
datapath
datapath modules with chisel
elfloader_dpi
ELF Loader DPI for systemverilog simulation environment
fputil
gznn_c
Neural Network in C
gzyIDE
Config files for my GitHub profile.
matmul_csr
CSR based SpMV
ParamMod
Parameterized Verilog Modules for many applications
perceptron
verilog implementation of perceptron
riscv-isa-sim
Spike, a RISC-V ISA Simulator
gzyIDE's Repositories
gzyIDE/fputil
gzyIDE/ParamMod
Parameterized Verilog Modules for many applications
gzyIDE/perceptron
verilog implementation of perceptron
gzyIDE/cbp-tage
TAGE implemented in cbp
gzyIDE/datapath
datapath modules with chisel
gzyIDE/elfloader_dpi
ELF Loader DPI for systemverilog simulation environment
gzyIDE/gznn_c
Neural Network in C
gzyIDE/gzyIDE
Config files for my GitHub profile.
gzyIDE/matmul_csr
CSR based SpMV
gzyIDE/riscv-isa-sim
Spike, a RISC-V ISA Simulator
gzyIDE/rust_perceptron
Rust practice
gzyIDE/SysvDevEnv
Template RTL development environment for SystemVerilog
gzyIDE/tvm-uma
TVM UMA practice
gzyIDE/xilinx_fpga_template
Xilinx fpga development environment template
gzyIDE/ZYNQ_PL_SDRAM_test
SDRAM Access test from PL logic