Pinned Repositories
-FIFO-Testbench
verify a FIFO design based on the provided RTL code “FIFO.v”
4-Bits-Full-Adder
The aim of this project is to design 4-bit Full Adder using different techniques (Ripple Carry, Carry LookAhead)
Complete-ASIC-Flow-of-I2C-communication-protocol
Design-and-optimization-of-fully-differential-discrete-time-2nd-order-sigma-delta-ADC
In this project, we aim to design and optimize a fully differential sigma-delta ADC that achieves exceptional performance in terms of noise shaping, signal-to-noise ratio (SNR), and bandwidth.
Design-of-an-RF-Front-End-of-a-Receiver-Chain
design and simulate the LNA and Mixer blocks independently to ensure their individual functionality. Subsequently, the two blocks are integrated and simulated together to validate their combined functionality and performance within the receiver chain
Design-Spartan6---DSP48A1-using-Vivado
Using Vivado to go through the design flow running elaboration, synthesis, implementation for all the designs making sure that there are no design check errors during the design flow..
Full-Custom_SDES
The primary objective of this project is to design and implement a Simplified Data Encryption Standard (S-DES) algorithm, which retains the essential features of the DES algorithm but with much smaller parameters.
Fully-Integrated-Folded-Cascode-OTA-with-Common-mode-feedback-network
Design Steps, Simulation, Analysis, and Layout verification of a Fully Integrated Folded Cascode OTA with Common mode feedback network using UMC 65nm technology
Graduation-project
Graduation Project
habibhossam
Config files for my GitHub profile.
habibhossam's Repositories
habibhossam/-FIFO-Testbench
verify a FIFO design based on the provided RTL code “FIFO.v”
habibhossam/4-Bits-Full-Adder
The aim of this project is to design 4-bit Full Adder using different techniques (Ripple Carry, Carry LookAhead)
habibhossam/Complete-ASIC-Flow-of-I2C-communication-protocol
habibhossam/Design-and-optimization-of-fully-differential-discrete-time-2nd-order-sigma-delta-ADC
In this project, we aim to design and optimize a fully differential sigma-delta ADC that achieves exceptional performance in terms of noise shaping, signal-to-noise ratio (SNR), and bandwidth.
habibhossam/Design-of-an-RF-Front-End-of-a-Receiver-Chain
design and simulate the LNA and Mixer blocks independently to ensure their individual functionality. Subsequently, the two blocks are integrated and simulated together to validate their combined functionality and performance within the receiver chain
habibhossam/Design-Spartan6---DSP48A1-using-Vivado
Using Vivado to go through the design flow running elaboration, synthesis, implementation for all the designs making sure that there are no design check errors during the design flow..
habibhossam/Full-Custom_SDES
The primary objective of this project is to design and implement a Simplified Data Encryption Standard (S-DES) algorithm, which retains the essential features of the DES algorithm but with much smaller parameters.
habibhossam/Fully-Integrated-Folded-Cascode-OTA-with-Common-mode-feedback-network
Design Steps, Simulation, Analysis, and Layout verification of a Fully Integrated Folded Cascode OTA with Common mode feedback network using UMC 65nm technology
habibhossam/Graduation-project
Graduation Project
habibhossam/habibhossam
Config files for my GitHub profile.
habibhossam/Verification-of-SPI-slave-IP-with-SystemVerilog
habibhossam/Microprocessor-Design
Microprocessor Design like SAP-1
habibhossam/Object_detection_model_for_smart_blind_stick
Object Detection Deep Learning Model for Smart Blind Stick
habibhossam/SPI-Slave-with-Single-Port-RAM
Designing SPI Slave with Single Port RAM using questasim and vivado.