Issues
- 0
Bytes & ASCII - incorrect info
#94 opened by abgros - 13
ePub build
#50 opened by mgarciaisaia - 9
Inclusion of IBM Z (mainframe) information.
#53 opened by vmdave9 - 5
Reach out to Chris Sawyer
#33 opened by maxwofford - 2
linux uppercaser not uppercaser
#77 opened by yancyribbens - 3
Query regarding contribution.
#67 opened by amandewatnitrr - 4
- 3
Syntax error
#59 opened by ospilos - 3
Better RISC-V section
#37 opened by TheThirdOne - 4
Is the code/text open source licensable?
#56 opened by xxuejie - 2
Typos
#49 opened by dcbrewster - 1
Feedback and Suggested Fixes
#47 opened by Welding-Torch - 1
Loop de Loop polish required
#41 opened by darkgray1981 - 2
Add 8086 assembly code example
#13 opened by ashwinexe - 1
Possible typo in uppercaser
#38 opened by webpigeon - 1
Typo in conditionals.md
#43 opened by m3rcurial - 5
Broken Tycoon Wiki link
#32 opened by quackduck - 1
Add Z80 assembly code example
#12 opened by jessicard - 1
Add ARM assembly code example
#10 opened by jessicard - 1
Add x86-64 AT&T syntax
#15 opened by jessicard - 3
Add 6502 assembly code example
#11 opened by jessicard - 1
Add README to RISC-V section
#18 opened by jessicard - 1
Add README to x86-64 Intel syntax section
#17 opened by jessicard