haikunliu

haikunliu's Stars

• CGCL-codes/YiTu

  YiTu is an easy-to-use runtime to fully exploit the hybrid parallelism of different hardwares (e.g., GPU) to efficiently support the execution of various kinds of graph algorithms (e.g., GNNs).

  Language:Python35135281

• cyjseagull/SHMA

  SHMA: Software-managed Caching for Hybrid DRAM/NVM Memory Architectures, implemented with zsim and nvmain hybrid simulators

  Language:C++5915434

• CGCL-codes/HSCC

  HSCC is implemented with zsim-nvmain hybrid simulator, it has achieved the following functions: (1) Memory management simulations (such as MemoryNode, Zone, Buddy Allocator etc.); (2) TLB, page table and reversed page table simulations; (3) Implementation of SHMA, a hierarchical hybrid DRAM/NVM memory system that brought DRAM caching issues into software level; (4) Multiple DRMA-NVM hybrid architecture supports.

  Language:C++527227

• CGCL-codes/HME

  HME a hybrid memory emulator for studying the performance and energy characteristics of upcoming NVM technologies. HME exploits features available in commodity NUMA architectures to emulate two kinds of memories: fast, local DRAM, and slower, remote NVM on other NUMA nodes. HME can emulates a wide range of NVM latencies and bandwidth by injecting different memory access delay on the remote NUMA nodes. To facilitate programmers and researchers in evaluating the impact of NVM on the application performance, a high-level programming interface is also provided to allocate memory from NVM or DRAM nodes.

  495618

• CGCL-codes/PRDMA

  pRDMA proposes persistent RPC designs. Persistent RPCs use several hardware-supported RDMA Flush primitives to decouple the data persisting from the complicated RPC processing. Also, pRDMA implements several RPC transmission models of state-of-the-art RPC work for performance comparison.

  Language:C7315

• CGCL-codes/HMCached

  HMCached is an in-memory K-V store built on a hybrid DRAM/NVM system. HMCached utilizes an application-level data access counting mechanism to identify frequently-accessed (hotspot) objects (i.e., K-V pairs) in NVM, and migrates them to fast DRAM to reduce the costly NVM accesses. We also propose an NVM-friendly index structure to store the frequently-updated portion of object metadata in DRAM, and thus further mitigate the NVM accesses. Moreover, we propose a benefit-aware memory reassignment policy to address the slab calcification problem in slab-based K-V store systems, and significantly improve the benefit gain from the DRAM.

  Language:C6402

• CGCL-codes/MHSim

  Language:C++6331

• CGCL-codes/FastResponse

  Language:C3301

• CGCL-codes/MorphStreamR

  Create this fork for Fault Tolerance

  Language:Java2200

• CGCL-codes/CLIMBER

  Language:Python120

• haikunliu/MHSim

  A Simulation Framework for Memristor-based Heterogeneous Computing Architectures

  Language:C++1000

• jgjdgdbd/CLIMBER

  Language:Python11