A tool that help to connect system verilog modules in SoC
This uses modified hdlparse libray (here)[https://github.com/hanhha/hdlparse] to parse IOs and parameters of modules.
A tool that help to connect system verilog modules in SoC
This uses modified hdlparse libray (here)[https://github.com/hanhha/hdlparse] to parse IOs and parameters of modules.