Pinned Repositories
ALADDIN
A pre-RTL, power-performance model for fixed-function accelerators
DeepRecSys
http://vlsiarch.eecs.harvard.edu/research/recommendation/
EdgeBERT
HW/SW co-design of sentence-level energy optimizations for latency-aware multi-task NLP inference
ESP_Systolic_Array_Accelerator
FlexASR
FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
gem5-aladdin
End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.
LLVM-Tracer
An LLVM pass to profile dynamic LLVM IR instructions and runtime values
RecPipe
smaug
SMAUG: Simulating Machine Learning Applications Using Gem5-Aladdin
Trireme
Trireme: Exploring Hierarchical Multi-Level Parallelism for Domain Specific Hardware Acceleration
Harvard Architecture, Circuits, and Compilers's Repositories
harvard-acc/gem5-aladdin
End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.
harvard-acc/ALADDIN
A pre-RTL, power-performance model for fixed-function accelerators
harvard-acc/LLVM-Tracer
An LLVM pass to profile dynamic LLVM IR instructions and runtime values
harvard-acc/DeepRecSys
http://vlsiarch.eecs.harvard.edu/research/recommendation/
harvard-acc/smaug
SMAUG: Simulating Machine Learning Applications Using Gem5-Aladdin
harvard-acc/EdgeBERT
HW/SW co-design of sentence-level energy optimizations for latency-aware multi-task NLP inference
harvard-acc/FlexASR
FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
harvard-acc/RecPipe
harvard-acc/ESP_Systolic_Array_Accelerator
harvard-acc/Trireme
Trireme: Exploring Hierarchical Multi-Level Parallelism for Domain Specific Hardware Acceleration
harvard-acc/smaug_docs
Documentation for SMAUG. Autogenerated, do not manually edit.