Pinned Repositories
3.90-M33
Contains the full source for 3.90 M33
album-detector
aosoc
axis_image_vip
ChipCMake
chisel-ahb
python-svlog
Verilog development framework with DPI-python verification utils
stocklab
stocklab-twse
vim-env
hchsiao's Repositories
hchsiao/axis_image_vip
hchsiao/python-svlog
Verilog development framework with DPI-python verification utils
hchsiao/stocklab-twse
hchsiao/chisel-ahb
hchsiao/3.90-M33
Contains the full source for 3.90 M33
hchsiao/album-detector
hchsiao/aosoc
hchsiao/ChipCMake
hchsiao/stocklab
hchsiao/vim-env
hchsiao/bazel-skylib
Common useful functions and rules for Bazel
hchsiao/breeze
Breeze is a numerical processing library for Scala.
hchsiao/Despertar-Del-Cementerio
Contains the full sources for DCv7
hchsiao/GoogleForm-AutoFill
AutoFill Google Form using Python
hchsiao/linode-manage
hchsiao/mcpat
An integrated power, area, and timing modeling framework for multicore and manycore architectures
hchsiao/memory_gen
hchsiao/multicore-test-harness
A multicore microprocessor test harness for measuring interference
hchsiao/openocd_jtag_dpi
TCP/IP controlled VPI JTAG Interface.
hchsiao/pssparser
ANTLR-based implementation of an Accellera PSS language parser with C++ and Python interfaces
hchsiao/raspberrypi
Raspberry Pi ARM based bare metal examples
hchsiao/raw-esp
Raw IP/Ethernet-forwarding firmware for ESP8266 WiFi module
hchsiao/riscv
hchsiao/riscv-isa-sim
Spike, a RISC-V ISA Simulator
hchsiao/riscv-openocd
Fork of OpenOCD that has RISC-V support
hchsiao/rules_antlr
ANTLR rules for Bazel
hchsiao/verible
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, and formatter.
hchsiao/verilog-ethernet
Verilog Ethernet components for FPGA implementation
hchsiao/zero-buggy
hchsiao/zero-riscy