RISC-V BFloat 16 extensions standardisation work.
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[About](#About)
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[Specification](#Specification)
This repository is used to develop standardisation proposals for Bfloat16 (Brain Float 16) instruction set extensions for the RISC-V architecture.
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Note: See the [main](https://github.com/riscv/riscv-bfloat16/tree/main) branch for the most up to date version.
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Note: These instructions are a work in progress. Their specifications will to change before being accepted as part of the RISC-V standard. While there are experimental encodings assigned to the proposed instructions, they should not be depended upon. They only exist to enable a toolchain and simulator flow. They will change.
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See the [project board](https://github.com/riscv/riscv-bfloat16/issues) for a list of on-going / open issues. ["How Can I Help?"](https://github.com/riscv/riscv-bfloat16/issues?q=is%3Aissue+is%3Aopen+label%3A%22help+wanted%22)
To see the latest draft release of the proposals, look at the [Releases](https://github.com/riscv/riscv-bfloat16/releases) tab of the [Github Repository](https://github.com/riscv/riscv-bfloat16).
Source code and supplementary information is found in the [doc/](doc/README.md) directory.